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參數資料
| 型號： | ADSP-2163BP-100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | RECTIFIER FAST-RECOVERY SINGLE 1.5A 100V 50A-ifsm 1V-vf 50ns 5uA-ir DO-15 1K/BULK |
| 中文描述： | 24-BIT, 25 MHz, OTHER DSP, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數： | 20/39頁 |
| 文件大?。?/td> | 243K |
| 代理商： | ADSP-2163BP-100 |
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REV. 0
ADSP-216x
SPECIFICATIONS
ADSP-2162/ADSP-2164/ADSP-2166
TEST CONDITIONS
Figure 18 shows voltage reference levels for ac measurements.
–20–
V
DD
2
OUTPUT
INPUT
V
DD
2
Figure 18.Voltage Reference LevelsforAC Measurements
(Except Output Enable/Disable)
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The out-
put disable time (t
DIS
) is the difference of t
MEASURED
and t
DECAY
,
as shown in Figure 19. The time t
MEASURED
is the interval from
when a reference signal reaches a high or low voltage level to
when the output voltages have changed by 0.5 V from the mea-
sured output high or low voltage.
The decay time, t
DECAY
, is dependent on the capacitative load,
C
L
, and the current load, i
L
, on the output pin. It can be ap-
proximated by the following equation:
t
C
V
i
DECAY
L
L
=
×
0 5
from which
t
DIS
=
t
MEASURED
–
t
DECAY
is calculated. If multiple pins (such as the data bus) are disabled,
the measurement value is that of the last pin to stop driving.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (t
ENA
) is the interval from when
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in Figure 19. If multiple pins (such as the data bus) are enabled,
the measurement value is that of the first pin to start driving.
2.0V
1.0V
t
ENA
REFERENCE
SIGNAL
OUTPUT
t
DECAY
V
(MEASURED)
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
t
DIS
t
MEASURED
V
OL
(MEASURED)
V
OH
(MEASURED) – 0.5V
V
OL
(MEASURED) +0.5V
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
V
(MEASURED)
V
(MEASURED)
Figure 19. Output Enable/Disable
TO
OUTPUT
PIN
50pF
I
OH
I
OL
V
DD
2
Figure 20. Equivalent Device Loading for AC
Measurements (Except Output Enable/Disable)
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|---|---|
| ADSP-2163BP-66 | DSP Microcomputers with ROM |
| ADSP-2163BS-100 | 100V 1A ULTRA FAST LOW-LOSS CONTROLLED AVALANCHE RECTIFIER, SMA US1 SERIES, DO- |
| ADSP-2163BS-66 | DSP Microcomputers with ROM |
| ADSP-2163KS-100 | DSP Microcomputers with ROM |
| ADSP-2163KS-66 | DSP Microcomputers with ROM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-2163BP-1002 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2163BP-66 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2163BP-662 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2163BS-100 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2163BS-1002 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
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