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參數資料
| 型號： | ADSP-2186L |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 中文描述： | 無電容，NMOS管，150mA的低壓差穩壓器的反向電流保護 |
| 文件頁數： | 9/34頁 |
| 文件大?。?/td> | 256K |
| 代理商： | ADSP-2186L |
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ADSP-2186L
–9–
REV. A
Boot Memory Select (
BMS
) Disable
The ADSP-2186L also lets you boot the processor from one
external memory space while using a different external memory
space for BDMA transfers during normal operation. You can
use the
CMS
to select the first external memory space for BDMA
transfers and
BMS
to select the second external memory space
for booting. The
BMS
signal can be disabled by setting Bit 3 of
the System Control Register to 1. The System Control Register
is illustrated in Figure 7.
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
15 14
13 12 11
10
9
8
7
6
5
4
3
2
1
0
DM (0 3FFF)
SYSTEM CONTROL REGISTER
1 = ENABLSPORT0 ENABLE
1 = ENABLSPORT1 ENABLE
SPORT1 CONFIGURE
1 = SERIAL PORT
0 = FI, FO,
IRQ0
,
IRQ1
, SCLK
PWAIT
WAIT STATES
BMS
ENABLE
0 = ENABLED, 1 = DISABLED
Figure 7. System Control Register
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The BDMA Control Register is
shown in Figure 8. The byte memory space consists of 256 pages,
each of which is 16K
×
8.
BDMA CONTROL
9
8
BMPAGE
BTYPE
BDIR
0 = LOAD FROM BM
1 = STORE TO BM
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
15 14 13 12 11 10
7
6
5
4
3
2
1
0
DM (0 3FE3)
Figure 8. BDMA Control Register
The byte memory space on the ADSP-2186L supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.
This allows up to a 4 meg
×
8 (32 megabit) ROM or RAM to be
used without glue logic. All byte memory accesses are timed by
the BMWAIT register.
Byte Memory DMA (BDMA, Full Memory Mode)
The byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space
while the processor is operating normally and steals only one
DSP cycle per 8-, 16- or 24-bit word transferred.
The BDMA circuit supports four different data formats, that are
selected by the BTYPE register field. The appropriate number
of 8-bit accesses is determined from the byte memory space to
build the word size selected. Table V shows the data formats sup-
ported by the BDMA circuit.
Table V. BDMA Data Formats
Internal
Memory Space
Program Memory
Data Memory
Data Memory
Data Memory
BTYPE
00
01
10
11
Word Size
24
16
8
8
Alignment
Full Word
Full Word
MSBs
LSBs
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address for
the on-chip memory involved with the transfer. The 14-bit BEAD
register specifies the starting address for the external byte memory
space. The 8-bit BMPAGE register specifies the starting page for
the external byte memory space. The BDIR register field selects
the direction of the transfer. Finally the 14-bit BWCOUNT
register specifies the number of DSP words to transfer and
initiates the BDMA circuit transfers.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is gener-
ated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.
The source or destination of a BDMA transfer will always be
on-chip program or data memory, regardless of the values of
Mode B, PMOVLAY or DMOVLAY.
When the BWCOUNT register is written with a nonzero value,
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to
external memory have priority over BDMA byte memory accesses.
The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue opera-
tions. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor and start execution at address 0 when
the BDMA accesses have completed.
Internal Memory DMA Port (IDMA Port; Host Memory Mode)
The IDMA Port provides an efficient means of communication
between a host system and the ADSP-2186L. The port is used
to access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot, however, be used to write directly to the DSP’s
memory-mapped control registers.
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is com-
pletely asynchronous and can be written to while the ADSP-
2186L is operating at full speed.
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