- 您現在的位置：買賣IC網 > PDF目錄374037 > ADSP-2195 (Analog Devices, Inc.) LM2991 Negative Low Dropout Adjustable Regulator; Package: CERDIP; No of Pins: 16; Qty per Container: 25; Container: Rail PDF資料下載
參數資料
| 型號： | ADSP-2195 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | LM2991 Negative Low Dropout Adjustable Regulator; Package: CERDIP; No of Pins: 16; Qty per Container: 25; Container: Rail |
| 中文描述： | DSP的微機 |
| 文件頁數： | 15/68頁 |
| 文件大?。?/td> | 951K |
| 代理商： | ADSP-2195 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
15
REV. PrA
For current information contact Analog Devices at 800/262-5643
ADSP-2195
September 2001
As indicated in
Table 6
, the OPMODE pin has a dual role,
acting as a boot mode select during reset and determining
SPORT or SPI operation at runtime. If the OPMODE pin
at reset is the opposite of what is needed in an application
during runtime, the application needs to set the OPMODE
bit appropriately during runtime prior to using the corre-
sponding peripheral.
Booting Modes
The ADSP-2195 has seven mechanisms (listed in
Table 6
)
for automatically loading internal program memory
after reset.
The OPMODE, BMODE1, and BMODE0 pins, sampled
during hardware reset, and three bits in the Reset Configu-
ration Register implement these modes:
Execute from memory external 16 bits—The memory
boot routine located in boot ROM memory space
executes a boot-stream-formatted program located at
address 0x10000 of boot memory space, packing 16-bit
external data into 24-bit internal data. The External Port
Interface is configured for the default clock multiplier
(128) and read waitstates (7).
Boot from EPROM—The EPROM boot routine located
in boot ROM memory space executes a boot-stream-for-
matted program located at address 0x00000 of boot
memory space, packing 8- or 16-bit external data into
24-bit internal data. The External Port Interface is con-
figured for the default clock multiplier (32) and read
waitstates (7).
Boot from Host—The (8- or 16-bit) Host downloads a
boot-stream-formatted program to internal or external
memory. The Host’s boot routine is located in internal
ROM memory space and uses the top 16 locations of
Page 0 program memory and the top 272 locations of
Page 0 data memory.
The internal boot ROM sets semaphore A (an IO register
within the host port) and then polls until the semaphore
is reset. Once detected, the internal boot ROM will remap
the interrupt vector table to Page 0 internal memory and
jump to address 0x0000 internal. From the point of view
of the host interface, an external host has full control of
the DSP's memory map. The Host has the freedom to
directly write internal memory, external memory, and
internal I/O memory space. The DSP core execution is
held off until the Host clears the semaphore register. This
strategy allows the maximum flexibility for the Host to
boot in the program and data code, by leaving it up to
the programmer.
Execute from memory external 8 bits (No Boot)—
execution starts from Page 1 of external memory space,
packing either 8- or 16-bit external data into 24-bit
internal data. The External Port Interface is configured
for the default clock multiplier (128) and read waitstates
(7).
Boot from UART—The Host downloads
boot-stream-formatted program using an autobaud
handshake sequence. The Host agent selects a baud rate
within the UART’s clocking capabilities. After a hardware
reset, the DSP’s UART transmits 0xFF values (eight bits
data, one start bit, one stop bit, no parity bit) until
detecting the start of the first memory block. The UART
boot routine is located in internal ROM memory space
and uses the top 16 locations of Page 0 program memory
and the top 272 locations of Page 0 data memory.
Boot from SPI, up to 4K bits—The SPI0 port uses the
SPI0SEL1 (reconfigured PF2) output pin to select a
single serial EPROM device, submits a read command at
address 0x00, and begins clocking consecutive data into
internal or external memory. Use only SPI-compatible
EPROMs of
≤
4K bit (12-bit address range). The SPI0
boot routine located in internal ROM memory space
executes a boot-stream-formatted program, using the top
16 locations of Page 0 program memory and the top 272
locations of Page 0 data memory. The SPI boot configu-
ration is SPIBAUD0=60 (decimal), CPHA=1, CPOL=1,
8-bit data, and MSB first.
Boot from SPI, from >4K bits to 512K bits—The SPI0
port uses the SPI0SEL1 (re-configured PF2) output pin
to select a single serial EPROM device, submits a read
command at address 0x00, and begins clocking consecu-
tive data into internal or external memory. Use only
SPI-compatible EPROMs of
≥
4K bit (16-bit address
range). The SPI0 boot routine located in internal ROM
memory space executes a boot-stream-formatted
program, using the top 16 locations of Page 0 program
memory and the top 272 locations of Page 0 data memory.
Table 6. Select Boot Mode (OPMODE, BMODE1, and
BMODE0)
O
B
B
Function
0
0
0
Execute from external memory 16 bits
(No Boot)
Boot from EPROM
Boot from Host
Reserved
Execute from external memory 8 bits
(No Boot)
Boot from UART
Boot from SPI, up to 4K bits
Boot from SPI, >4K bits up to
512K bits
0
0
0
1
0
1
1
0
1
0
1
0
1
1
1
0
1
1
1
0
1
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-2195MBCA-140X | LM2991 Negative Low Dropout Adjustable Regulator; Package: CERDIP; No of Pins: 16; Container: Rail |
| ADSP-2195MKST-160X | LM2991 Negative Low Dropout Adjustable Regulator; Package: TO-263; No of Pins: 5; Qty per Container: 45; Container: Rail |
| ADSP-2196 | DSP Microcomputer |
| ADSP-2196MBCA-140X | DSP Microcomputer |
| ADSP-2196MBST-140X | DSP Microcomputer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-2195MBCA-140 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 24-Bit 140MHz 140MIPS 144-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:16-BIT,140 MIPS, 2.5V, 80KBYTES RAM - Bulk |
| ADSP-2195MBST-140 | 功能描述:IC DSP CONTROLLER 16BIT 144LQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:ADSP-21xx 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，FCBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-2195MKCA-160 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 24-Bit 160MHz 160MIPS 144-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:16-BIT,160 MIPS, 2.5V, 80KBYTES RAM - Bulk |
| ADSP-2195MKST-160 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 24-Bit 160MHz 160MIPS 144-Pin LQFP 制造商:Analog Devices 功能描述:IC MICROCOMPUTER 16-BIT |
| adsp-2196mbca-140 | 制造商:Analog Devices 功能描述: |
發布緊急采購，3分鐘左右您將得到回復。