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參數資料
| 型號： | ADSP-2195 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | LM2991 Negative Low Dropout Adjustable Regulator; Package: CERDIP; No of Pins: 16; Qty per Container: 25; Container: Rail |
| 中文描述： | DSP的微機 |
| 文件頁數： | 52/68頁 |
| 文件大小： | 951K |
| 代理商： | ADSP-2195 |
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For current information contact Analog Devices at 800/262-5643
ADSP-2195
September 2001
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
52
REV. PrA
Output Drive Currents
Figure 27
shows typical I-V characteristics for the output
drivers of the ADSP-2195. The curves represent the current
drive capability of the output drivers as a function of output
voltage.
Power Dissipation
Total power dissipation has two components, one due to
internal circuitry and one due to the switching of external
output drivers. Internal power dissipation is dependent on
the instruction execution sequence and the data operands
involved. Using the current current-versus-operation infor-
mation in
Table 23
, designers can estimate the
ADSP-2195’s internal power supply (V
DDINT
) input current
for a specific application, according to the formula in
Figure 28
.
The external component of total power dissipation is caused
by the switching of output pins. Its magnitude depends on:
The number of output pins that switch during each cycle
(O)
The maximum frequency at which they can switch (f)
Their load capacitance (C)
Their voltage swing (V
DD
)
and is calculated by the formula in
Figure 29
.
Figure 27. ADSP-2195 Typical Drive Currents
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Table 23. ADSP-2195 Operation Types Versus Input Current
Activity
I
DD
(mA)
1
CCLK = 80 MHz
I
DD
(mA)
1
CCLK = 160 MHz
Core
Peripheral
Core
Peripheral
Power down
2
0
0
0
0
Idle 1
3
0
3
0
5
Idle 2
4
0
30
0
60
Typical
5
95
30
184
60
Peak
6
112
30
215
60
1
Test conditions: V
DD
= 2.50 V; HCLK (peripheral clock) frequency = CCLK/2 (core clock/2) frequency; T
AMB
= 25 oC.
2
PLL, Core, peripheral clocks, and CLKIN are disabled.
3
PLL is enabled and Core and peripheral clocks are disabled.
4
Core CLK is disabled and peripheral clock is enabled. This is a power- down interrupt mode. The timer can be used to generate an interrupt to enable the
Core clock.
5
All instructions execute from internal memory. 100% of the instructions are MAC with dual operand addressing, with changing data fetched using a linear
address sequence, and 50% of the instructions move data from PM to a data register.
6
All instructions execute from internal memory. 50% of the instructions are repeat MACs with dual operand addressing, with changing data fetched using
a linear address sequence.
Figure 28. I
DDINT
Calculation
I
DDINT
%Typical
I
DD-TYPICAL
×
(
)
=
%Idle
I
DD-IDLE
×
(
)
%Powerdown
I
DD-PWRDWN
×
(
)
+
+
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