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參數(shù)資料
型號: ADUC702
廠商: Analog Devices, Inc.
英文描述: 5 AMP MINIATURE POWER RELAY
中文描述: 精密模擬微控制器的12位模擬I / O,ARM7TDMI的微控制器
文件頁數(shù): 4/80頁
文件大小: 840K
代理商: ADUC702
ADuC702x Series
Preliminary Technical Data
Parameter
ANALOG OUTPUTS
Output Voltage Range_0
Ouput Voltage Range_1
Output Voltage Range_2
Output Impedance
DAC AC CHARACTERISTICS
Voltage Output Settling Time
Voltage Output Settling Time
Digital to Analog Glitch Energy
COMPARATOR
Input Offset Voltage
Input Bias Current
Input Voltage Range
Input Capacitance
Hysteresis
Response Time
Rev. PrB | Page 4 of 80
ADuC702x
0 to DACREF
0 to 2.5V
0 to DACV
DD
10
10
15
TBD
±10
5
AGND to AV
DD
-1.2
7
5
10
1
10
TBD
-1.5
±3
2.79
3.07
±2.5
0
TBD
10,000
30
±10
±1
10
0.4
2.0
Unit
V typ
V typ
V typ
typ
μs typ
μs typ
nV-sec typ
mV
nA typ
Vmin/Vmax
pF typ
mV min
mv max
μs min
μs max
mV typ
mV/°C typ
°C typ
V
V
% max
ms min
ms max
Cycles min
Years min
μA max
μA typ
pF typ
V max
V min
Test Conditions/Comments
DACREF range: DACGND to DACV
DD
DAC Output buffered
DAC Output unbuffered
I LSB change at major carry
Hysteresis can be turned on or off via the
CMPHYST bit in the CMPCON register
Response time may be modified via the CMPRES
bits in the CMPCON register
TEMPERATURE SENSOR
Voltage Output at 25°C
Voltage TC
Accuracy
POWER SUPPLY MONITOR (PSM)
IOV
DD
Trip Point Selection
Power Supply Trip Point Accuracy
Watchdog Timer (WDT)
4
Timeout Period
Two selectable Trip Points
Of the selected nominal Trip Point Voltage
Flash/EE MEMORY
Endurance
10
Data Retention
11
Digital Inputs
Input Leakage Current
Input Capacitance
Logic Inputs
4
VINL, Input Low Voltage
VINH, Input High Voltage
Logic Outputs
T
J
= 55°C
All digital inputs including XTAL1 and XTAL2
All Logic inputs including XTAL1 and XTAL2
VOH, Output High Voltage
VOL, Output Low Voltage
12
MCU CLOCK RATE
IOV
DD
– 400mV
0.4
355.5
45.5
TBD
TBD
TBD
TBD
V min
V max
kHz min
MHz max
I
SOURCE
= 1.6mA
I
SINK
= 1.6mA
8 programmable core clock selections within this
range
Core Clock = TBD MHz
STARTUP TIME
At Power-On
From Idle Mode
From Power-Down Mode
Programmable Logic Array (PLA)
Propagation Delay
ns typ
From input pin to output pin
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