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參數資料
| 型號： | ADUC702 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 5 AMP MINIATURE POWER RELAY |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁數： | 65/80頁 |
| 文件大小： | 840K |
| 代理商： | ADUC702 |
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Preliminary Technical Data
ADuC702x Series
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
Rev. PrB | Page 65 of 80
There are 24 interrupt sources on the ADuC702x which are
controlled by the Interrupt Controller. Most interrupts are
generated from the on-chip peripherals like ADC, UART, etc.
and two additional interrupt sources are generated from
external interrupt request pins, XIRQ0 and XIRQ1. The
ARM7TDMI CPU core will only recognise interrupts as one of
two types, a normal interrupt request IRQ and a fast interrupt
request FIQ. All the interrupts can be masked separately.
The control and configuration of the interrupt system is
managed through nine interrupt-related registers, four
dedicated to IRQ, four dedicated to FIQ. An additional MMR is
used to select the programmed interrupt source. The bits in
each IRQ and FIQ registers represent the same interrupt source
as described in Table 58.
Table 58: IRQ/FIQ MMRs bit description
Bit
0
1
Description
All interrupts OR’ed
SWI:
not used in IRQEN/CLR
and FIQEN/CLR
Timer 0
Timer 1
Wake Up timer – Timer 2
Watchdog timer – Timer 3
Flash control
ADC channel
PLL lock
I
2
C0 Slave
I
2
C0 Master
I
2
C1 Master
SPI Slave
SPI Master
UART
External IRQ0
Comparator
PSM
External IRQ1
PLA IRQ0
PLA IRQ1
External IRQ2
External IRQ3
PWM trip
PWM sync
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
IRQ
The IRQ is the exception signal to enter the IRQ mode of the
processor. It is used to service general purpose interrupt
handling of internal and external events.
The four 32-bit registers dedicated to IRQ are:
-
IRQSIG
, reflects the status of the different IRQ sources. If a
peripheral generate an IRQ signal, the corresponding bit in
the IRQSIG will be set, otherwise it is cleared. The IRQSIG
bits are cleared when the interrupt in the particular
peripheral is cleared. All IRQ sources can be masked in the
IRQEN MMR. IRQSIG is read-only.
-
IRQEN
, provides the value of the current enable mask. When
bit is set to 1, the source request is enabled to create an IRQ
exception. When bit is set to 0, the source request is disabled
or masked which will not
create an IRQ exception.
-
IRQCLR
, (write-only register) allows clearing the IRQEN
register in order to mask an interrupt source. Each bit set to 1
will clear the corresponding bit in the IRQEN register
without affecting the remaining bits. The pair of registers
IRQEN and IRQCLR allows independent manipulation of
the enable mask without requiring an atomic read-modify-
write.
-
IRQSTA
, (read-only register) provides the current enabled
IRQ source status. When set to 1 that source should generate
an active IRQ request to the ARM7TDMI core. There is no
priority encoder or interrupt vector generation. This function
is implemented in software in a common interrupt handler
routine. All 32 bits are logically OR’ed to create the IRQ signal
to the ARM7TDMI core.
FIQ
The FIQ (Fast Interrupt reQuest) is the exception signal to
enter the FIQ mode of the processor. It is provided to service
data transferor communication channel tasks with low latency.
The FIQ interface is identical to the IRQ interface providing the
second level interrupt (highest priority). Four 32-bit registers
are dedicated to FIQ, FIQSIG, FIQEN, FIQCLR and FIQSTA.
Bit 31 to 1 of FIQSTA are logically OR’ed to create the FIQ
signal to the core and the bit 0 of both the FIQ and IRQ
registers (FIQ source).
The logic for FIQEN and FIQCLR will not allow an interrupt
source to be enabled in both IRQ and FIQ masks. A bit set to ‘1’
in FIQEN will, as a side-effect, clear the same bit in IRQEN. A
bit set to ‘1’ in IRQEN will, as a side-effect, clear the same bit in
FIQEN. An interrupt source can be disabled in both IRQEN
and FIQEN masks.
Programmed interrupts
As the programmed interrupts are non-mask-able, they are
controlled by another register, SWICFG, which write into both
IRQSTA and IRQSIG registers or/and FIQSTA and FIQSIG
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