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| 型號(hào)： | ADUC702 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 5 AMP MINIATURE POWER RELAY |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁數(shù)： | 76/80頁 |
| 文件大小： | 840K |
| 代理商： | ADUC702 |
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ADuC702x Series
Preliminary Technical Data
digital and analog sections, as illustrated in Figure 41c.
Rev. PrB | Page 76 of 80
b.
DGND
AGND
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS
HERE
c.
GND
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS
HERE
DGND
PLACE ANALOG
COMPONENTS HERE
a.
AGND
PLACE DIGITAL
COMPONENTS HERE
Figure 41:. System grounding schemes
In all of these scenarios, and in more complicated real-life
applications, keep in mind the flow of current from the supplies
and back to ground. Make sure the return paths for all currents
are as close as possible to the paths the currents took to reach
their destinations. For example, do not power components on
the analog side of Figure 41b with IOV
DD
since that would force
return currents from IOV
DD
to flow through AGND. Also, try
to avoid digital currents flowing under analog circuitry, which
could happen if the user placed a noisy digital chip on the left
half of the board in Figure 41c. Whenever possible, avoid large
discontinuities in the ground plane(s) (such as are formed by a
long trace on the same layer), since they force return signals to
travel a longer path. And of course, make all connections to the
ground plane directly, with little or no trace separating the pin
from its via to ground.
If the user plans to connect fast logic signals (rise/fall time < 5
ns) to any of the ADuC702x’s digital inputs, add a series
resistor to each relevant line to keep rise and fall times longer
than 5 ns at the ADuC702x input pins. A value of 100
or
200
is usually sufficient to prevent high speed signals from
coupling capacitively into the ADuC702x and affecting the
accuracy of ADC conversions.
CLOCK OSCILLATOR
The clock source for the ADuC702x can be generated by the
internal PLL or by an external clock input. To use the internal
PLL, connect a 32.768kHz parallel resonant crystal between
XCLKI and XCLKO and connect a capacitor from each pin to
ground as shown Figure 42 This crystal allows the PLL to lock
correctly to give a frequency of 45.088MHz. If no external
crystal is present, the internal oscillator will be used to give a
frequency of 45.088MHz
±
5% typically.
12pF
XCLKI
XCLKO
32.768kHz
TO INTERNAL
PLL
ADuC7026
12pF
Figure 42: external parallel resonant crystal connections
To use an external source clock input instead of the PLL, bit 1
and bit 0 of PLLCON must be modified. The external clock
uses pin 17, XCLK.
TO FREQUENCY
DIVIDER
ADuC7026
XCLK
EXTERNAL
CLOCK
SOURCE
XCLKI
Figure 43:connecting an external clock source
Whether using the internal PLL or an external clock source, the
ADuC702x’s specified operational clock speed range is 50kHz
to 20MHz to ensure correct operation of the analog peripherals
and Flash/EE.
POWER-ON RESET OPERATION
An internal POR (Power-On Reset) is implemented on the
ADuC702x. For LV
DD
below 1.98 V, the internal POR will hold
the ADuC702x in reset. As LV
DD
rises above 1.98 V, an internal
timer will time out for typically 128 ms before the part is
released from reset. The user must ensure that the power
supply IOV
DD
has reached a stable 2.7 V minimum level by this
time. Likewise on power-down, the internal POR will hold the
ADuC702x in reset until LV
DD
has dropped below 1.98V.
Figure 44 illustrates the operation of the internal POR in detail.
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