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參數資料
型號: ADUC814
廠商: Analog Devices, Inc.
英文描述: MicroConverter, Small Package 12-Bit ADC with Embedded Flash MCU
中文描述: MicroConverter的,小包裝12位ADC,嵌入式閃存MCU
文件頁數: 37/72頁
文件大小: 846K
代理商: ADUC814
ADuC814
ON-CHIP PLL
The ADuC814 is intended for use with a 32.768 kHz watch
crystal. An on-board PLL locks onto a multiple (512) of this
32.768kHz frequency to provide a stable 16.777216 MHz clock
for the system. The core can operate at this frequency or at
binary submultiples of it to allow power saving in cases where
maximum core performance is not required. The default core
clock is the PLL clock divided by 8 (2
CD
= 2
3
) or 2.097152 MHz.
The PLL is controlled via the PLLCON special function register.
Rev. A | Page 37 of 72
PLLCON
SFR Address
Power-On Default
Bit Addressable
PLL Control Register
D7H
03H
No
OSC_PD
LOCK
---
---
FINT
CD2
CD1
CD0
Table 13. PLLCON SFR Bit Designations
Bit No.
Name
7
OSC_PD
Description
Oscillator Power-Down Bit.
Set by the user to halt the 32 kHz oscillator in power-down mode.
Cleared by the user to enable the 32 kHz oscillator in power-down mode. This feature allows the oscillator to
continue clocking the TIC even in power-down mode.
PLL Lock Bit. This is a read-only bit.
Set automatically at power-on to indicate that the PLL loop is correctly tracking the crystal clock. If the external
crystal becomes subsequently disconnected, the PLL rails and the core halts.
Cleared automatically at power-on to indicate that the PLL is not correctly tracking the crystal clock. This may be due
to the absence of a crystal clock or an external crystal at power-on. In this mode, the PLL output is 16.78 MHz ± 20%.
Reserved. Should be written with 0.
Reserved. Should be written with 0.
Fast Interrupt Response Bit.
Set by the user to enable the response to any interrupt to be executed at the fastest core clock frequency, regardless
of the configuration of the CD2–CD0 bits (see below). Once user code has returned from an interrupt, the core
resumes code execution at the core clock selected by the CD2–CD0 bits.
Cleared by the user to disable the fast interrupt response feature.
CPU (Core Clock) Divider Bits.
This number determines the frequency at which the microcontroller core operates.
CD2
CD1
CD0
Core Clock Frequency (MHz)
0
0
0
16.777216
0
0
1
8.388608
0
1
0
4.194304
0
1
1
2.097152 (Default Core Clock Frequency)
1
0
0
1.048576
1
0
1
0.524288
1
1
0
0.262144
1
1
1
0.131072
6
LOCK
5
4
3
---
---
FINT
2
1
0
CD2
CD1
CD0
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相關代理商/技術參數
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