
ADuC814
ADuC814 HARDWARE DESIGN CONSIDERATIONS
This section outlines some key hardware design considerations
for integrating the ADuC814 into any hardware system.
Rev. A | Page 60 of 72
CLOCK OSCILLATOR
As described earlier, the core clock frequency for the ADuC814
is generated from an on-chip PLL that locks onto a multiple
(512 times) of 32.768 kHz. The latter is generated from an
internal clock oscillator. To use the internal clock oscillator,
connect a 32.768 kHz parallel resonant crystal between XTAL1
and XTAL2 pins (Pins 26 and 27) as shown in Figure 54.
As shown in the typical external crystal connection diagram in
Figure 54, two internal 12 pF capacitors are provided on-chip.
These are connected internally, directly to the XTAL1 and
XTAL2 pins. The total input capacitances at both pins is
detailed in the Specifications table. The value of the total load
capacitance required for the external crystal should be the value
recommended by the crystal manufacturer for use with that
specific crystal. In many cases, because of the on-chip capacitors,
additional external load capacitors are not required.
ADuC814
TO PLL
12pF
12pF
XTAL1
XTAL2
0
Figure 54. External Parallel Resonant Crystal Connections
As an alternative to providing two separate power supplies,
AV
DD
can be kept quiet by placing a small series resistor and/or
ferrite bead between it and DV
DD
, and then decoupling AV
DD
separately to ground. An example of this configuration is shown
in Figure 56. With this configuration, other analog circuitry
(such as op amps and voltage reference) can be powered from
the AV
DD
supply line as well.
POWER SUPPLIES
The ADuC814’s operational power supply voltage range is 2.7 V
to 5.5 V. Although the guaranteed data sheet specifications are
given only for power supplies within 2.7 V to 3.3 V or 4.5 V to
5.5 V, (±10% of the nominal level), the chip can function equally
well at any power supply level between 2.7 V and 5.5 V.
Users should separate analog and digital power supply pins
(AV
DD
and DV
DD
) and allow AV
DD
to be kept relatively free of
noisy digital signals often present on the system DV
DD
line. In
this mode, the part can also operate with split supplies as long
as the supply voltages are within 0.3 V of each other. A typical
split-supply configuration is show in Figure 55.
DV
DD
AGND
AV
DD
–
+
0.1
μ
F
10
μ
F
ANALOG SUPPLY
10
μ
F
DGND
0.1
μ
F
DIGITAL SUPPLY
–
+
ADuC814
0
Figure 55. External Dual-Supply Connections
DV
DD
AGND
AV
DD
DGND
DIGITAL SUPPLY
–
+
BEAD
1.6
0.1
μ
F
0.1
μ
F
10
μ
F
10
μ
F
ADuC814
0
Figure 56. External Single-Supply Connections
Notice that in both Figure 55 and Figure 56, a large value
(10 μF) reservoir capacitor sits on DV
DD
and a separate 10 μF
capacitor sits on AVDD. Also, local small-value (0.1 μF) capacitors
are located at each V
DD
pin of the chip. As per standard design
practice, be sure to include all of these capacitors, and ensure
that the smaller capacitors are closest to each AV
DD
pin with
trace lengths as short as possible. Connect the ground terminal
of each of these capacitors directly to the underlying ground
plane. Finally, note that, at all times, the analog and digital ground
pins on the ADuC814 should be referenced to the same system
ground reference point.
POWER CONSUMPTION
The CORE values given represent the current drawn by DV
DD
,
while the rest (ADC and DAC) are pulled by the AV
DD
pin and
can be disabled in software when not in use. The other on-chip
peripherals (such as watchdog timer and power supply monitor)
consume negligible current and are therefore lumped in with
the CORE operating current here. Of course, the user must add
any currents sourced by the parallel and serial I/O pins, and that
sourced by the DAC, in order to determine the total current
needed at the ADuC814’s supply pins. Also, current drawn from
the DVDD supply increases by approximately 5 mA during the
Flash/EE erase and program cycles.