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參數資料
| 型號： | ADUC848BCP8-5 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Cable Gland (Clamp); Connector Shell Size:10SL, 12S; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Thread Size:5/8-24; Approval Categories:MIL-C-5015; Series:97 RoHS Compliant: No |
| 中文描述： | 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, QCC56 |
| 封裝： | 8 X 8 MM, MO-220-VLLD-2, LFCSP-56 |
| 文件頁數： | 12/108頁 |
| 文件大小： | 1109K |
| 代理商： | ADUC848BCP8-5 |
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ADuC845/ADuC847/ADuC848
Pin No:
52-MQFP
7
8
9
Rev. A | Page 12 of 108
Pin No:
56-CSP
7
8
9
Mnemonic
REFIN
REFIN+
P1.4/AIN5
Type
1
I
I
I
Description
External Differential Reference Input, Negative Terminal.
External Differential Reference Input, Positive Terminal.
On power-on default, P1.4/AIN5 is configured as the AIN5 analog input.
AIN5 can be used as a pseudo differential input when used with AINCOM or as
the positive input of a fully differential pair when used with AIN6.
P1.0 has no digital output driver. It can function as a digital input for which 0
must be written to the port bit. As a digital input, this pin must be driven high or
low externally.
On power-on default, P1.5/AIN6 is configured as the AIN6 analog input.
AIN6 can be used as a pseudo differential input when used with AINCOM or as
the negative input of a fully differential pair when used with AIN5.
P1.1 has no digital output driver. It can function as a digital input for which 0
must be written to the port bit. As a digital input, this pin must be driven high or
low externally.
On power-on default, P1.6/AIN7 is configured as the AIN7 analog input.
AIN7 can be used as a pseudo differential input when used with AINCOM or as
the positive input of a fully differential pair when used with AIN8. One or both
current sources can also be configured at this pin.
P1.6 has no digital output driver. It can, however, function as a digital input for
which 0 must be written to the port bit. As a digital input, this pin must be
driven high or low externally.
On power-on default, P1.7/AIN8 is configured as the AIN8 analog input.
AIN8 can be used as a pseudo differential input when used with AINCOM or as
the negative input of a fully differential pair when used with AIN7. One or both
current sources can also be configured at this pin.
P1.7 has no digital output driver. It can, however, function as a digital input for
which 0 must be written to the port bit. As a digital input, this pin must be
driven high or low externally.
All analog inputs can be referred to this pin, provided that a relevant pseudo
differential input mode is selected. This pin also functions as an alternative pin
out for the DAC.
The voltage output from the DAC, if enabled, appears at this pin.
AIN9 can be used as a pseudo differential analog input when used with AINCOM
or as the positive input of a fully differential pair when used with AIN10 (CSP
version only).
AIN10 can be used as a pseudo differential analog input when used with
AINCOM or as the negative input of a fully differential pair when used with AIN9
(CSP version only).
Reset Input. A high level on this pin for 16 core clock cycles while the oscillator is
running resets the device. This pin has an internal weak pull-down and a Schmitt
trigger input stage.
P3.0 to P3.7 are bidirectional port pins with internal pull-up resistors. Port 3 pins
that have 1s written to them are pulled high by the internal pull-up resistors,
and in that state can be used as inputs. As inputs, Port 3 pins being pulled
externally low source current because of the internal pull-up resistors. When
driving a 0-to-1 output transition, a strong pull-up is active for one core clock
period of the instruction cycle.
Port 3 pins also have the various secondary functions described below.
Receiver Data for UART Serial Port.
Transmitter Data for UART Serial Port.
External Interrupt 0. This pin can also be used as a gate control input to Timer 0.
External Interrupt 1. This pin can also be used as a gate control input to Timer 1.
Timer/Counter 0 External Input.
Timer/Counter 1 External Input.
External Data Memory Write Strobe. This pin latches the data byte from Port 0
into an external data memory.
10
10
P1.5/AIN6
I
11
11
P1.6/AIN7/IEXC1
I/O
12
12
P1.7/AIN8/IEXC2
I/O
13
13
AINCOM/DAC
I/O
14
----
14
15
DAC
AIN9
O
I
----
16
AIN10
I
15
17
RESET
I
16–19
22–25
18–21
24–27
P3.0–P3.7
I/O
16
17
18
19
22
23
24
18
19
20
21
24
25
26
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
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