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| 型號： | ADUC848BCP8-5 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Cable Gland (Clamp); Connector Shell Size:10SL, 12S; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Thread Size:5/8-24; Approval Categories:MIL-C-5015; Series:97 RoHS Compliant: No |
| 中文描述： | 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, QCC56 |
| 封裝： | 8 X 8 MM, MO-220-VLLD-2, LFCSP-56 |
| 文件頁數(shù)： | 33/108頁 |
| 文件大小： | 1109K |
| 代理商： | ADUC848BCP8-5 |
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ADuC845/ADuC847/ADuC848
can be taken. When the resulting voltage measured is full scale,
the transducer has gone open circuit. When the voltage measured
is 0 V, this indicates that the transducer has gone short circuit.
The current sources work over the normal absolute input
voltage range specifications.
Rev. A | Page 33 of 108
REFERENCE DETECT CIRCUIT
The main and auxiliary (ADuC845 only) ADCs can be
configured to allow the use of the internal band gap reference or
an external reference that is applied to the REFIN± pins by
means of the XREF0/1 bit in the Control Registers AD0CON2
and AD1CON (ADuC845 only). A reference detection circuit is
provided to detect whether a valid voltage is applied to the
REFIN± pins. This feature arose in connection with strain-gage
sensors in weigh scales where the reference and signal are
provided via a cable from the remote sensor. It is desirable to
detect whether the cable is disconnected. If either of the pins is
floating or if the applied voltage is below a specified threshold, a
flag (NOXREF) is set in the ADC status register (ADCSTAT),
conversion results are clamped, and calibration registers are not
updated if a calibration is in progress.
Note that the reference detect does not look at REFIN2± pins.
If, during either an offset or gain calibration, the NOEXREF bit
becomes active, indicating a incorrect V
REF
, updating the relevant
calibration register is inhibited to avoid loading incorrect data
into these registers, and the appropriate bits in ADCSTAT (ERR0
or ERR1) are set. If the user needs to verify that a valid
reference is in place every time a calibration is performed, the
status of the ERR0 and ERR1 bits should be checked at the end
of every calibration cycle.
SINC FILTER REGISTER (SF)
The number entered into the SF register sets the decimation
factor of the Sinc
3
filter for the ADC. See Table 28 and Table 29.
The range of operation of the SF word depends on whether
ADC chop is on or off. With chop disabled, the minimum SF
word is 3 and the maximum is 255. This gives an ADC through-
put rate from 16.06 Hz to 1.365 kHz. With chop enabled, the
minimum SF word is 13 (all values lower than 13 are clamped
to 13) and the maximum is 255. This gives an ADC throughput
rate of from 5.4 Hz to 105 Hz. See the f
ADC
equation in the ADC
description preceding section.
An additional feature of the Sinc
3
filter is a second notch filter
positioned in the frequency response at 60 Hz. This gives
simultaneous 60 Hz rejection to whatever notch is defined by
the SF filter. This 60 Hz filter is enabled via the REJ60 bit in the
ADCMODE register (ADCMODE.6). The notch is valid only
for SF words ≥ 68; otherwise, ADC errors occur, and, in fact, the
notch is best used with an SF word of 82d giving simultaneous
50 Hz and 60 Hz rejection. This function is useful only with an
ADC clock (modulator rate) of 32.768 kHz. During calibration,
the current (user-written) value of the SF register is used.
Σ-
MODULATOR
A Σ- ADC usually consists of two main blocks, an analog
modulator, and a digital filter. For the ADuC845/ADuC847/
ADuC848, the analog modulator consists of a difference
amplifier, an integrator block, a comparator, and a feedback
DAC as shown in Figure 16.
INTEGRATOR
COMPARATOR
DIFFERENCE
AMP
ANALOG
INPUT
HIGH
FREQUENCY
BIT STREAM
TO DIGITAL
FILTER
DAC
0
Figure 16. Σ- Modulor Simplified Block Diagram
In operation, the analog signal is fed to the difference amplifier
along with the output from the feedback DAC. The difference
between these two signals is integrated and fed to the comparator.
The output from the comparator provides the input to the feed-
back DAC so the system functions as a negative feedback loop
that tries to minimize the difference signal. The digital data that
represents the analog input voltage is contained in the duty
cycle of the pulse train appearing at the output of the comparator.
This duty cycle data can be recovered as a data-word by using a
subsequent digital filter stage. The sampling frequency of the
modulator loop is many times higher than the bandwidth of the
input signal. The integrator in the modulator shapes the
quantization noise (that results from the analog-to-digital
conversion) so that the noise is pushed toward one-half of the
modulator frequency.
DIGITAL FILTER
The output of the ∑- modulator feeds directly into the digital
filter. The digital filter then band-limits the response to a
frequency significantly lower than one-half of the modulator
frequency. In this manner, the 1-bit output of the comparator is
translated into a band-limited, low noise output from the part.
The ADuC845/ADuC847/ADuC848 filter is a low-pass, Sinc
3
or
[(SINx)/x]
3
filter whose primary function is to remove the
quantization noise introduced at the modulator. The cutoff
frequency and decimated output data rate of the filter are
programmable via the SF (Sinc filter) SFR as listed in Table 28
and Table 29.
Figure 22, Figure 23, Figure 24, and Figure 25 show the frequency
response of the ADC, yielding an overall output rate of 16.6 Hz
with chop enabled and 50 Hz with chop disabled. Also detailed
in these plots is the effect of the fixed 60 Hz drop-in notch filter
(REJ60 bit, ADCMODE.6). This fixed filter can be enabled or
disabled by setting or clearing the REJ60 bit in the ADCMODE
register (ADCMODE.6). This 60 Hz drop-in notch filter can be
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