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參數資料
| 型號： | ADUC848BCP8-5 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Cable Gland (Clamp); Connector Shell Size:10SL, 12S; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Thread Size:5/8-24; Approval Categories:MIL-C-5015; Series:97 RoHS Compliant: No |
| 中文描述： | 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, QCC56 |
| 封裝： | 8 X 8 MM, MO-220-VLLD-2, LFCSP-56 |
| 文件頁數： | 89/108頁 |
| 文件大小： | 1109K |
| 代理商： | ADUC848BCP8-5 |
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ADuC845/ADuC847/ADuC848
Rev. A | Page 89 of 108
SPI Interrupt
If the SERIPD bit in the PCON SFR is set, an SPI interrupt,
if enabled, wakes up the part from power-down mode. The
CPU services the SPI interrupt. The RETI at the end of the
ISR returns the core to the next instruction after the one
that enabled power-down.
INT0 Interrupt
If the INT0PD bit in the PCON SFR is set, an external
interrupt 0, if enabled, wakes up the part from power-
down. The CPU services the interrupt. The RETI at the end
of the ISR returns the core to the next instruction after the
one that enabled power-down.
Wake-Up from Power-Down Latency
Even with the 32 kHz crystal enabled during power-down, the
PLL takes some time to lock after a wake-up from power-down.
Typically, the PLL takes about 1 ms to lock. During this time,
code executes, but not at the specified frequency. Some opera-
tions, for example, UART communications, require an accurate
clock to achieve the specified 50 Hz/60 Hz rejection from the
ADCs. Therefore, it is advisable to wait until the PLL has locked
before proceeding with normal code execution. The following
code can be used to wait for the PLL to lock:
WAITFORLOCK: MOV A, PLLCON
JNB ACC.6, WAITFORLOCK
If the crystal is powered down during power-down, an additional
delay is associated with the startup of the crystal oscillator
before the PLL can lock. Typically taking about 150 ms, 32 kHz
crystals are inherently slow to oscillate. During this time before
lock, code executes, but the exact frequency of the clock cannot
be guaranteed. For any timing-sensitive operations, it is
recommended to wait for lock by using the lock bit in PLLCON
as shown previously.
An alternative way of saving power in power-down mode
is to slow down the core clock by using the CD bits in the
PLLCON register.
GROUNDING AND BOARD LAYOUT
RECOMMENDATIONS
As with all high resolution data converters, special attention
must be paid to grounding and PC board layout of ADuC845/
ADuC847/ADuC848-based designs in order to achieve
optimum performance from the ADCs and DAC.
Although the parts have separate pins for analog and digital
ground (AGND and DGND), the user must not tie these to
separate ground planes unless the two ground planes are
connected together very close to the part as shown in the
simplified example in Figure 67a. In systems where digital and
analog ground planes are connected together somewhere else
(at the system’s power supply, for example), they cannot be
connected again near the part since a ground loop would result.
In these cases, tie the AGND and DGND pins of the part to the
analog ground plane, as shown in Figure 67b. In systems with
only one ground plane, ensure that the digital and analog
components are physically separated onto separate halves of the
board such that digital return currents do not flow near analog
circuitry and vice versa. The parts can then be placed between
the digital and analog sections, as shown in Figure 67c.
In all of these scenarios, and in more complicated real-life
applications, keep in mind the flow of current from the supplies
and back to ground. Make sure that the return paths for all
currents are as close as possible to the paths the currents took to
reach their destinations. For example, do not power components
on the analog side of Figure 67b with DV
DD
since that would
force return currents from DV
DD
to flow through AGND. Also,
try to avoid digital currents flowing under analog circuitry,
which could happen if the user placed a noisy digital chip on
the left half of the board in Figure 67c. Whenever possible,
avoid large discontinuities in the ground plane(s) (such as are
formed by a long trace on the same layer), since they force
return signals to travel a longer path. Make all connections
directly to the ground plane, with little or no trace separating
the pin from its via to ground.
DGND
AGND
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS
HERE
GND
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS
HERE
DGND
a.
AGND
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS
HERE
b.
c.
0
Figure 67. System Grounding Schemes
If the user plans to connect fast logic signals (rise/fall time < 5 ns)
to any of the ADuC845/ADuC847/ADuC848’s digital inputs,
add a series resistor to each relevant line to keep rise and fall
times longer than 5 ns at the parts input pins. A value of 100
or 200 is usually sufficient to prevent high speed signals from
coupling capacitively into the part and affecting the accuracy of
ADC conversions.
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