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| 型號(hào)： | ADUC848BCP8-5 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Cable Gland (Clamp); Connector Shell Size:10SL, 12S; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Thread Size:5/8-24; Approval Categories:MIL-C-5015; Series:97 RoHS Compliant: No |
| 中文描述： | 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, QCC56 |
| 封裝： | 8 X 8 MM, MO-220-VLLD-2, LFCSP-56 |
| 文件頁(yè)數(shù)： | 68/108頁(yè) |
| 文件大小： | 1109K |
| 代理商： | ADUC848BCP8-5 |
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ADuC845/ADuC847/ADuC848
POWER SUPPLY MONITOR
The power supply monitor, once enabled, monitors the DV
DD
and AV
DD
supplies on the parts. It indicates when any of the
supply pins drop below one of four user-selectable voltage trip
points from 2.63 V to 4.63 V. For correct operation of the power
supply monitor function, AV
DD
must be equal to or greater than
2.63 V. Monitor function is controlled via the PSMCON SFR. If
enabled via the IEIP2 SFR, the monitor interrupts the core by
using the PSMI bit in the PSMCON SFR. This bit is not cleared
until the failing power supply returns above the trip point for at
least 250 ms.
Rev. A | Page 68 of 108
The monitor function allows the user to save working registers
to avoid possible data loss due to the low supply condition, and
also ensures that normal code execution does not resume until a
Table 43. PSMCON SFR Bit Designations
Bit No.
Name
Description
7
CMPD
DV
DD
Comparator Bit.
This read-only bit directly reflects the state of the DV
DD
comparator.
Read 1 indicates that the DV
DD
supply is above its selected trip point.
Read 0 indicates that the DV
DD
supply is below its selected trip point.
6
CMPA
AV
DD
Comparator Bit.
This read-only bit directly reflects the state of the AV
DD
comparator.
Read 1 indicates that the AV
DD
supply is above its selected trip point.
Read 0 indicates that the AV
DD
supply is below its selected trip point.
5
PSMI
Power Supply Monitor Interrupt Bit.
Set high by the MicroConverter if either CMPA or CMPD is low, indicating low analog or digital supply. The PSMI
bit can be used to interrupt the processor. Once CMPD and/or CMPA returns (and remains) high, a 250 ms
counter is started. When this counter times out, the PSMI interrupt is cleared. PSMI can also be written by the
user. However, if either comparator output is low, it is not possible for the user to clear PSMI.
DV
DD
Trip Point Selection Bits.
A 5 V part has no valid PSM trip points. If the DV
DD
supply falls below the 4.63 V point, the part resets (POR). For a
3 V part, all relevant PSM trip points are valid. The 3 V POR trip point is 2.63 V (fixed).
These bits select the DV
DD
trip point voltage as follows:
TPD1
TPD0
Selected DV
DD
Trip Point (V)
0
0
4.63
0
1
3.08
1
0
2.93
1
1
2.63
AV
DD
Trip Point Selection Bits. These bits select the AV
DD
trip point voltage as follows:
TPA1
TPA0
Selected AV
DD
Trip Point (V)
0
0
4.63
0
1
3.08
1
0
2.93
1
1
2.63
0
PSMEN
Power Supply Monitor Enable Bit.
Set to 1 by the user to enable the power supply monitor circuit.
Cleared to 0 by the user to disable the power supply monitor circuit.
safe supply level is well established. The supply monitor is also
protected against spurious glitches triggering the interrupt
circuit.
Note that the 5 V part has an internal POR trip level of 4.63 V,
which means that there are no usable DV
DD
PSM trip levels on
the 5 V part. The 3 V part has a POR trip level of 2.63 V
following a reset and initialization sequence, allowing all
relevant PSM trip points to be used.
PSMCON—Power Supply Monitor Control Register
SFR Address:
Power-On Default:
Bit Addressable:
DFH
DEH
No
4, 3
TPD1, TPD0
2, 1
TPA1, TPA0
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