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參數資料
型號: ADUC848BCP8-5
廠商: ANALOG DEVICES INC
元件分類: 微控制器/微處理器
英文描述: Cable Gland (Clamp); Connector Shell Size:10SL, 12S; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Thread Size:5/8-24; Approval Categories:MIL-C-5015; Series:97 RoHS Compliant: No
中文描述: 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, QCC56
封裝: 8 X 8 MM, MO-220-VLLD-2, LFCSP-56
文件頁數: 29/108頁
文件大小: 1109K
代理商: ADUC848BCP8-5
ADuC845/ADuC847/ADuC848
ADC Noise Performance with Chop Enabled (CHOP = 0)
Rev. A | Page 29 of 108
Table 10, Table 11, Table 12, and Table 13 show the output rms
noise and output peak-to-peak resolution in bits (rounded to
the nearest 0.5 LSB) for some typical output update rates for the
ADuC845, ADuC847, and ADuC848. The numbers are typical
and are generated at a differential input voltage of 0 V and a
common-mode voltage of 2.5 V. The output update rate is
selected via the SF7 to SF0 bits in the SF filter register. It is
important to note that the peak-to-peak resolution figures
represent the resolution for which there is no code flicker
within a 6-sigma limit.
The output noise comes from two sources. The first source is
the electrical noise in the semiconductor devices (device noise)
Table 10. ADuC845 and ADuC847 Typical Output RMS Noise (μV) vs. Input Range and Update Rate with Chop Enabled
SF Word
Data Update Rate (Hz)
±20 mV
±40 mV
13
105.03
1.75
1.30
23
59.36
1.25
0.95
27
50.56
1.0
1.0
69
19.79
0.63
0.68
255
5.35
0.31
0.38
used in the implementation of the modulator. The second
source is quantization noise, which is added when the analog
input is converted to the digital domain. The device noise is at a
low level and is independent of frequency. The quantization
noise starts at an even lower level but rises rapidly with increasing
frequency to become the dominant noise source.
The numbers in the tables are given for the bipolar input ranges.
For the unipolar ranges, the rms noise numbers are in the same
range as the bipolar figures, but the peak-to-peak resolution is
based on half the signal range, which effectively means losing
1 bit of resolution.
Input Range
±160 mV
1.5
0.94
0.85
0.7
0.32
±80 mV
1.65
1.08
0.85
0.52
0.34
±320 mV
2.1
1.0
1.13
0.61
0.4
±640 mV
3.1
1.87
1.56
1.1
0.45
±1.28 V
7.15
3.24
2.9
1.3
0.68
±2.56 V
13.3
7.1
3.6
2.75
1.22
Table 11. ADuC845 and ADuC847 Typical Peak-to-Peak Resolution (Bits) vs. Input Range and Update Rate with Chop Enabled
SF Word
Data Update Rate (Hz)
±20 mV
±40 mV
±80 mV
13
105.03
12
13
14
23
59.36
12
13.5
14.5
27
50.56
12.5
13.5
15
69
19.79
13
14
15.5
255
5.35
14.5
15
16
Input Range
±160 mV
15
15.5
16
16
17
±320 mV
15.5
16.5
16.5
17.5
18
±640 mV
16
16.5
17
17.5
18.5
±1.28 V
16
17
17
18
19
±2.56 V
16
16.5
17.5
18
19.5
Table 12. ADuC848 Typical Output Noise (μV) vs. Input Range and Update Rate with Chop Enabled
SF Word
Data Update Rate (Hz)
±20 mV
13
105.03
1.75
23
59.36
1.25
27
50.56
1.0
69
19.79
0.63
255
5.35
0.31
Input Range
±160 mV
1.5
0.94
0.85
0.7
0.32
±40 mV
1.30
0.95
1.0
0.68
0.38
±80 mV
1.65
1.08
0.85
0.52
0.34
±320 mV
2.1
1.0
1.13
0.61
0.4
±640 mV
3.1
1.87
1.56
1.1
0.45
±1.28 V
7.15
3.24
2.9
1.3
0.68
±2.56 V
13.3
7.1
3.6
2.75
1.22
Table 13. ADuC848 Typical Peak-to-Peak Resolution (Bits) vs. Input Range and Update Rate with Chop Enabled
SF Word
Data Update Rate (Hz)
±20 mV
±40 mV
13
105.03
12
13
23
59.36
12
13.5
27
50.56
12.5
13.5
69
19.79
13
14
255
5.35
14.5
15
Input Range
±160 mV
15
15.5
16
16
16
±80 mV
14
14.5
15
15.5
16
±320 mV
15.5
16
16
16
16
±640 mV
16
16
16
16
16
±1.28 V
16
17
16
16
16
±2.56 V
16
16
16
16
16
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