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參數(shù)資料
| 型號(hào)： | ADUC848BCP8-5 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Cable Gland (Clamp); Connector Shell Size:10SL, 12S; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Thread Size:5/8-24; Approval Categories:MIL-C-5015; Series:97 RoHS Compliant: No |
| 中文描述： | 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, QCC56 |
| 封裝： | 8 X 8 MM, MO-220-VLLD-2, LFCSP-56 |
| 文件頁(yè)數(shù)： | 13/108頁(yè) |
| 文件大小： | 1109K |
| 代理商： | ADUC848BCP8-5 |
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ADuC845/ADuC847/ADuC848
Pin No:
52-MQFP
25
Rev. A | Page 13 of 108
Pin No:
56-CSP
27
Mnemonic
P3.7/RD
Type
1
Description
External Data Memory Read Strobe. This pin enables the data from an external
data memory to Port 0.
Digital Supply Voltage.
Digital Ground.
20, 34, 48
21, 35, 47
22, 36, 51
23, 37,
38, 50
28
DV
DD
DGND
S
S
26
SCLK (I
2
C)
I/O
Serial Interface Clock for the I
2
C Interface. As an input, this pin is a Schmitt-
triggered input. A weak internal pull-up is present on this pin unless it is
outputting logic low. This pin can also be controlled in software as a digital
output pin.
Serial Data Pin for the I
2
C Interface. As an input, this pin has a weak internal pull-
up present unless it is outputting logic low.
Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have
1s written to them are pulled high by the internal pull-up resistors, and in that
state can be used as inputs. As inputs, Port 2 pins being pulled externally low
source current because of the internal pull-up resistors. Port 2 emits the middle
and high-order address bytes during accesses to the 24-bit external data
memory space.
Port 2 pins also have the various secondary functions described below.
Serial Interface Clock for the SPI Interface. As an input this pin is a Schmitt-
triggered input. A weak internal pull-up is present on this pin unless it is
outputting logic low.
Serial Master Output/Slave Input Data for the SPI Interface. A strong internal
pull-up is present on this pin when the SPI interface outputs a logic high. A
strong internal pull-down is present on this pin when the SPI interface outputs a
logic low.
Master Input/Slave Output for the SPI Interface. A weak pull-up is present on this
input pin.
Slave Select Input for the SPI Interface. A weak pull-up is present on this pin.
For both package options, this pin can also be used to provide a clock input to
Timer 2. When enabled, Counter 2 is incremented in response to a negative
transition on the T2 input pin.
Control Input to Timer 2. When enabled, a negative transition on the T2EX input
pin causes a Timer 2 capture or reload event.
If the PWM is enabled, the PWM0 output appears at this pin.
If the PWM is enabled, the PWM1 output appears at this pin.
If the PWM is enabled, an external PWM clock can be provided at this pin.
Input to the Crystal Oscillator Inverter.
Output from the Crystal Oscillator Inverter. See the Hardware Design
Considerations section for a description.
External Access Enable, Logic Input. When held high, this input enables the
device to fetch code from internal program memory locations 0000H to F7FFH.
No external program memory access is available on the ADuC845, ADuC847, or
ADuC848. To determine the mode of code execution, the EA pin is sampled at
the end of an external RESET assertion or as part of a device power cycle. EA can
also be used as an external emulation I/O pin, and therefore the voltage level at
this pin must not be changed during normal operation because this might
cause an emulation interrupt that halts code execution.
Program Store Enable, Logic Output. This function is not used on the ADuC845,
ADuC847, or ADuC848. This pin remains high during internal program execution.
PSEN can also be used to enable serial download mode when pulled low
through a resistor at the end of an external RESET assertion or as part of a device
power cycle.
Address Latch Enable, Logic Output. This output is used to latch the low byte
(and page byte for 24-bit data address space accesses) of the address to external
memory during external data memory access cycles. It can be disabled by
setting the PCON.4 bit in the PCON SFR.
27
29
SDATA
I/O
28–31,
36–39
30–33,
39–42
P2.0–P2.7
I/O
28
30
P2.0/SCLOCK (SPI)
29
31
P2.1/MOSI
30
32
P2.2/MISO
31
33
P2.3/SS/T2
36
39
P2.4/T2EX
37
38
39
32
33
40
41
42
34
35
P2.5/PWM0
P2.6/PWM1
P2.7/PWMCLK
XTAL1
XTAL2
I
O
40
43
EA
41
44
PSEN
O
42
45
ALE
O
Footnotes at end of table.
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