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參數資料
| 型號： | ADV601 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 視頻Codec |
| 英文描述： | Low Cost Multiformat Video Codec |
| 中文描述： | 低成本多格式視頻解碼器 |
| 文件頁數： | 17/52頁 |
| 文件大小： | 606K |
| 代理商： | ADV601 |
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ADV601
–17–
REV. 0
DRAM Interface Pins
Name
Pins
I/O
Description
DDAT[15:0]
16
I/O
DRAM Data Bus. The ADV601 uses these pins for 16-bit data read/write
operations to the external 256K
×
16-bit DRAM. (The operation of the DRAM
interface is fully automatic and controlled by internal functionality of the
ADV601.) These pins are compatible with 30 pF loads.
DRAM Address Bus. The ADV601 uses these pins to form the multiplexed
row/column address lines to the external DRAM. (The operation of the DRAM
interface is fully automatic and controlled by internal functionality of the
ADV601.) These pins are compatible with 30 pF loads.
DRAM Row Address Strobe. This pin is compatible with 30 pF loads.
DRAM Column Address Strobe. This pin is compatible with 30 pF loads.
DRAM Write Enable. This pin is compatible with 30 pF loads.
Note that the ADV601 does not have a DRAM
OE
pin. Tie the DRAM’s
OE
pin to ground.
DADR[8:0]
9
O
RAS
CAS
WE
1
1
1
O
O
O
Serial Port Pins and Timing
DSP Interface Pins
Name
Pins
I/O
Description
TXD
1
O
Serial Transmit Data. Connect this pin to an optional, external DSP’s serial
interface RXData pin. If no DSP is present, this pin may be left unconnected.
This pin is compatible with 30 pF loads.
The TXD pin is for serial data output from the ADV601. Serial data consists of
16-bit words that are transferred most-significant-bit first.
Note that the Mode Control register must be set to indicate whether or not the
external DSP is present.
Serial Receive Data. Connect this pin to an optional, external DSP’s serial
interface TXData pin. If no DSP is present, tie this pin to ground. This pin is
compatible with 30 pF loads.
The RXD pin is for serial data input to the ADV601. Serial data consists of 16-
bit words that are transferred most-significant-bit first.
Note that the Mode Control register must be set to indicate whether or not the
external DSP is present.
Serial Data Clock (VCLK/4). Connect this pin to an optional, external DSP’s
serial interface SCLK pin. If no DSP is present, this pin may be left uncon-
nected. This pin is compatible with 30 pF loads.
The TCLK pin is the serial interface clock. Communication in and out of the
ADV601 requires bits of data to be transmitted after a rising edge of TCLK, and
sampled on a falling edge of TCLK. The DSP must be in external bit clock mode
to use TCLK correctly. The codec drives the TCLK frequency at 1/4 VCLK.
Some typical VCLK and TCLK frequencies are as follows:
VCLK
TCLK (= 1/4 VCLK)
27 MHz
6.75 MHz
29.5 MHz
7.375 MHz
24.54 MHz
6.135 MHz
Note that the Mode Control register must be set to indicate whether or not the
external DSP is present.
RXD
1
I
TCLK
1
O
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