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參數資料
| 型號： | ADV601 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 視頻Codec |
| 英文描述： | Low Cost Multiformat Video Codec |
| 中文描述： | 低成本多格式視頻解碼器 |
| 文件頁數： | 49/52頁 |
| 文件大小： | 606K |
| 代理商： | ADV601 |
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ADV601
–49–
REV. 0
DSP Interface Timing
The diagram in this section shows transfer timing for one set of video statistics and calculated bin widths as they pass through the
ADV601’s DSP interface. Whenever an ADV601’s serial port is inactive, the codec’s TXD pin is three-stated and the codec ignores
the state of the RXD pin. Figure 41 illustrates the ADV601 serial interface’s signal, sample and frame relationships for the transmit
and receive modes.
Table XXXVII. DSP Read and Write Transfer Timing Parameters
Parameter
Description
Min
Max
Unit
t
TCLK_DIRQ_D
t
TCLK_DIRQ_OH
t
VCLK_TCLK_D
t
TCLK_TF_D
t
TCLK_TF_OH
t
TCLK_TXD_D
t
TCLK_TXD_OH
t
TCLK_RF_S
t
TCLK_RF_H
t
TCLK_RXD_S
t
TCLK_RXD_H
DIRQ
Signal, Transfer-Receive Cycle Start, Delay
DIRQ
Signal, Transfer-Receive Cycle End, Output Hold
TCLK
Signal, Referenced to VCLK, Delay
TF Signal, Transfer Frame Reference to TCLK, Delay
TF Signal, Transfer Frame Reference to TCLK, Output Hold
TXD Sample, Transfer Data, Delay (at 27 MHz VCLK)
TXD Sample, Transfer Data, Output Hold
RF Signal, Receive Frame Referenced to TCLK, Setup
RF Signal, Receive Frame Referenced to TCLK, Hold
RXD Sample, Receive Data, Setup
RXD Sample, Receive Data, Hold (at 27 MHz VCLK)
N/A
3
N/A
N/A
2
N/A
2
2
105
2
16.8
2
4
N/A
11
3
N/A
24.2
1
N/A
N/A
N/A
N/A
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1
Maximum t
TCLK_TXD_D
varies with VCLK according to the formula: t
TCLK_TXD_D
(MAX)
= 0.5 (VCLK Period) +4.7.
2
Minimum t
TCLK_RXD_H
varies with VCLK according to the formula: t
TCLK_RXD_H
(MIN)
= 1.5 (VCLK Period) –36.
(O)
DIRQ
DSP CALCULATES BIN WIDTHS
FROM VIDEO STATISTICS
(I) VCLK
(O) TCLK
TCLK PERIOD = 4
·
VCLK PERIOD
FIFTY-TWO 16-BIT WORDS TRANSFERRED BY THE ADV601
-- ADV601 REGISTERS 0x06 AND 0x80 THROUGH 0xB2
EIGHTY-FOUR 16-BIT WORDS TRANSFERRED BY THE DSP
-- ADV601 REGISTERS 0x100 THROUGH 0x153
(O) TF
(O) TXD
t
TCLK_TXD_OH
TCLK_TXD_D
t
TCLK_RF_S
t
TCLK_RXD_H
t
TCLK_RXD_S
(I) RF
(I) RXD
t
TCLK_DIRQ_OH
t
TCLK_DIRQ_D
t
TCLK_TF_D
t
VCLK_TCLK_D
t
TCLK_RF_H
t
TCLK_TF_OH
Figure 41. DSP Read and Write Transfer Timing
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