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參數資料
| 型號： | ADV601 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 視頻Codec |
| 英文描述： | Low Cost Multiformat Video Codec |
| 中文描述： | 低成本多格式視頻解碼器 |
| 文件頁數： | 46/52頁 |
| 文件大?。?/td> | 606K |
| 代理商： | ADV601 |
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ADV601
–46–
REV. 0
Table XXXIV. Host (Indirect Address, Indirect Data, and Interrupt Mask/Status) Write Timing Parameters
Parameter
Description
Min
Max
Unit
t
WR_D_WRC
t
WR_D_PWA
t
WR_D_PWD
t
ADR_D_WRS
t
ADR_D_WRH
t
DATA_D_WRS
t
DATA_D_WRH
t
WR_D_RDT
t
ACK_D_WRD
t
ACK_D_WROH
WR
Signal, Direct Register, Write Cycle Time (at 27 MHz VCLK)
WR
Signal, Direct Register, Pulse Width Asserted (at 27 MHz VCLK)
WR
Signal, Direct Register, Pulse Width Deasserted (at 27 MHz VCLK)
ADR Bus, Direct Register, Write Setup
ADR Bus, Direct Register, Write Hold
DATA Bus, Direct Register, Write Setup
DATA Bus, Direct Register, Write Hold
WR
Signal, Direct Register, Read Turnaround (After a Write) (at 27 MHz VCLK)
ACK
Signal, Direct Register, Write Delay (at 27 MHz VCLK)
ACK
Signal, Direct Register, Write Output Hold
N/A
1
N/A
1
5
2
2
–20
0
35.6
2
8.6
11
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
182.1
3, 4
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1
WR
input must be asserted (low) until ACK is asserted (low).
2
Minimum t
WR_D_RDT
varies with VCLK according to the formula: t
WR_D_RDT (MIN)
= 0.8 (VCLK Period) +7.4.
3
Maximum t
varies with VCLK according to the formula: t
= 4.3 (VCLK Period) +14.8.
4
During STATS_R deasserted (low) conditions, t
ACK_D_WRD
may be as long as 52 VCLK periods.
VALID
VALID
VALID
VALID
(I) ADR,
BE
,
CS
(I)
WR
(I) DATA
(O)
ACK
(I)
RD
t
ADR_D_WRS
t
DATA_D_WRS
t
ACK_D_WROH
t
WR_D_WRC
t
WR_D_PWA
t
WR_D_PWD
t
ADR_D_WRH
t
DATA_D_WRH
t
ACK_D_WRD
t
WR_D_RDT
Figure 38. Host (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Write Transfer Timing
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相關代理商/技術參數 |
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