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參數資料
| 型號： | FEDL7204-001DIGEST-01 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 元件分類： | Codec |
| 英文描述： | The ML7204-001 is a speech CODEC for VoIP. |
| 中文描述： | 在ML7204 - 001是一種VoIP語音編解碼器。 |
| 文件頁數： | 27/42頁 |
| 文件大小： | 792K |
| 代理商： | FEDL7204-001DIGEST-01 |
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FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
27/42
GPIOB[5:0]
This is a general-purpose I/O port B[5:0]. (Provided for 100-pin packages only.)
GPIOC[7:0]
This is a general-purpose I/O port C[7:0]. (Provided for 100-pin packages only.)
CLKSEL
This is an input-output control input pin of SYNC and BCLK. The pin controls input when it is set to “0” and
output when it is set to “1”.
SYNC
This is a 8 kHz synchronous signal I/O pin of PCM signals. When CLKSEL is “0”, constantly input an 8 kHz
clock synchronized with BCLK. When CLKSEL is “1”, this pin outputs an 8 kHz clock synchronized with
BCLK. When the SYNC frame control register (SYNC_SEL) is “0”, long frame synchronization is specified
and when the register is “1”, short frame synchronization is specified.
BCLK
This is a shift clock I/O pin of a PCM signal.
When CLKSEL is “0”, clock input synchronized with SYNC is necessary. When G.711 is selected, input a
clock of 64 kHz to 2.048 MHz and when 16-bit linear is selected, input a clock of 128 kHz to 2.048 MHz.
When CLKSEL is “1”, this pin outputs a clock of 2.048 MHz synchronized with SYNC.
(Remarks) Table 2 shows the input-output control of SYNC and BCLK and the frequencies.
Table 2 SYNC and BCLK Input-Output Control
CLKSEL
SYNC
BCLK
Always input a clock after start of power supply.
When G.711 is selected, input a clock of 64 kHz to 2.048
MHz.
When 16-bit linear is selected, input a clock of 128 kHz to
2.048 MHz.
Output
(8 kHz)
(2.048 MHz)
PCMO
This is a PCM signal output pin. A PCM signal is output synchronized with the rise of BCLK or SYNC.
For the output from PCMO, data is output to only the applicable time slot section according to the selected
coding format and the setting of the time slot position and other sections are set to a high-impedance state. If a
PCM interface is not used, PCMO is set to a high impedance state.
(Note)
Be sure to connect a pull-up resistor externally to the PCMO pin, because the pin is an open drain output pin.
Do not use a pull-up voltage greater than the digital power supply voltage (DVDD).
PCMI
This is a PCM signal input pin. The signal is shifted at falling of BCLK and is input from MSB.
If a PCM interface is not used, fix the input to “0” or “1”.
Remarks
“0”
Input
(8 kHz)
Input
(64 kHz to
2048 kHz)
“1”
Output
At power down, “L” is output.
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