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參數(shù)資料
| 型號(hào)： | GS9092 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| 中文描述： | GS9092 GenLINX - R的第三270Mb / s的串行SDI和DVB - ASI在內(nèi) |
| 文件頁數(shù)： | 9/58頁 |
| 文件大小： | 608K |
| 代理商： | GS9092 |
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GS9092 Data Sheet
28202 - 2
September 2005
9 of 58
23, 25, 26
STAT[0:2]
Synchronous
with PCLK or
WR_CLK
Input/O
utput
MULTI FUNCTION I/O PORT
Signal levels are LVCMOS / LVTTL compatible.
Programmable multi-function I/O. By programming the bits in the
IO_CONFIG register, each pin can act as an output for one of the
following signals:
H
V
F
FIFO_FULL
FIFO_EMPTY
Each pin may also act as an input for an external H, V, or F signal if the
DETECT_TRS pin is set LOW by the application layer
These pins are set to certain default values depending on the
configuration of the device and the internal FIFO mode selected. See
Programmable Multi-function I/O on page 46
for details.
24, 28, 42
IO_GND
Non
Synchronous
Input
Power
Ground connection for digital I/O. Connect to GND.
30
WR_CLK
Input
FIFO WRITE CLOCK
Signal levels are LVCMOS / LVTTL compatible.
The application layer clocks the parallel data into the device on the
rising edge of WR_CLK when the internal FIFO is configured for video
mode or DVB-ASI mode.
NOTE: If this pin is unused it should be pulled up to GND.
31
WR_RESET
Synchronous
with
WR_CLK
Input
FIFO WRITE RESET
Signal levels are LVCMOS / LVTTL compatible.
Valid input only when the device is in SMPTE mode (SMPTE_BYPASS
= HIGH, DVB-ASI = LOW) and the internal FIFO is configured for video
mode (
Video Mode on page 23
).
A HIGH to LOW transition will reset the FIFO write pointer to address
zero of the memory.
NOTE: If this pin is unused it should be pulled up to GND.
32 - 41
DIN[0:9]
Synchronous
with
WR_CLK
or PCLK
Input
PARALLEL VIDEO DATA BUS
Signal levels are LVCMOS / LVTTL compatible.
When the internal FIFO is enabled and configured for either video
mode or DVB-ASI mode, parallel data will be clocked into the device on
the rising edge of WR_CLK.
When the internal FIFO is in bypass mode, parallel data will be clocked
into the device on the rising edge of PCLK.
DIN9 is the MSB and DIN0 is the LSB.
44
PCLK
Input
PIXEL CLOCK INPUT
Signal levels are LVCMOS / LVTTL compatible.
27MHz parallel clock input.
46
RSV
–
–
Reserved. Do Not Connect.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS9092-CNE3 | GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| GSC9620 | P-CHANNEL ENHANCEMENT MODE POWER MOSFET |
| GSD2004S-V-GS08 | DIODE 0.225 A, 300 V, 2 ELEMENT, SILICON, SIGNAL DIODE, TO-236AB, ROHS COMPLIANT, PLASTIC PACKAGE-3, Signal Diode |
| GSD2004S-V-GS18 | DIODE 0.225 A, 300 V, 2 ELEMENT, SILICON, SIGNAL DIODE, TO-236AB, ROHS COMPLIANT, PLASTIC PACKAGE-3, Signal Diode |
| GSD2004W-V-GS18 | DIODE 0.225 A, 300 V, SILICON, SIGNAL DIODE, ROHS COMPLIANT, PLASTIC PACKAGE-2, Signal Diode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS9092A | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GS9092A GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| GS9092A_10 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GenLINX III 270Mb/s Serializer for SDI and DVB-ASI |
| GS9092ACNE3 | 功能描述:RF, RFID, WIRELESS RoHS:是 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類型:串行 輸出類型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:管件 |
| GS9092ACNTE3 | 制造商:Semtech Corporation 功能描述:270Mb/s Transmitter for SDI & ASI |
| GS9092CNE3 | 制造商:Gennum Corporation 功能描述: |
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