- 您現在的位置：買賣IC網 > PDF目錄385345 > GS9092ACNE3 (Gennum Corporation) GS9092A GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI PDF資料下載
參數資料
| 型號： | GS9092ACNE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS9092A GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| 中文描述： | GS9092A GenLINX - R的第三270Mb / s的串行SDI和DVB - ASI在內 |
| 文件頁數： | 24/59頁 |
| 文件大小： | 614K |
| 代理商： | GS9092ACNE3 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁
GS9092A Data Sheet
34715 - 0
February 2006
24 of 59
The application layer must start writing the first active pixel of the line into location
zero of memory. Therefore, the user should use the WR_RESET pin to reset the
FIFO write pointer prior to writing to the device.
NOTE: The BLANK signal must not be asserted in video mode.
3.3.2 DVB-ASI Mode
The internal FIFO is in DVB-ASI mode when the application layer sets the
FIFO_EN pin HIGH and the FIFO_MODE[1:0] bits in the IOPROC_DISABLE
register are configured to 01b. By default, the FIFO_MODE[1:0] bits are set to 01b
by the device whenever the DVB_ASI pin is set HIGH (i.e. the device is in DVB-ASI
mode); however, the application layer may program the FIFO_MODE[1:0] bits as
required.
Figure 3-3
shows the input and output signals of the FIFO when it is configured for
DVB-ASI Mode.
Figure 3-3: FIFO in DVB-ASI Mode
When operating in DVB-ASI mode, the GS9092A's FIFO can be used for clock rate
interchange operation. 8-bit MPEG data as well as a K_IN control signal must be
written to the FIFO by the application layer. The MPEG data and control signal can
be simultaneously clocked into the FIFO at any rate using the rising edge of the
WR_CLK pin.
The 8-bit MPEG data stream may consist of only MPEG packets, or both MPEG
packets and special characters (such as the K28.5 stuffing characters). The
application layer must set K_IN HIGH whenever a special character is present in
the data stream, otherwise it should be LOW. The GS9092A uses the K_IN signal
to determine whether or not a given byte in the FIFO is an MPEG packet that needs
8b/10b encoded.
The INSSYNCIN pin should be grounded while operating the FIFO in DVB-ASI
mode.
The GS9092A internally reads the data out of the FIFO at the PCLK rate and adds
the necessary number of stuffing characters based on the FIFO status flags.
WR_CLK
K_IN
FIFO
(DVB-ASI Mode)
RD_CLK (PCLK)
Internal
Application Interface
8-bit MPEG Data
FIFO_FULL
FIFO_EMPTY
8-bit MPEG Data
K_IN
相關PDF資料 |
PDF描述 |
|---|---|
| GS9092 | GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| GS9092-CNE3 | GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| GSC9620 | P-CHANNEL ENHANCEMENT MODE POWER MOSFET |
| GSD2004S-V-GS08 | DIODE 0.225 A, 300 V, 2 ELEMENT, SILICON, SIGNAL DIODE, TO-236AB, ROHS COMPLIANT, PLASTIC PACKAGE-3, Signal Diode |
| GSD2004S-V-GS18 | DIODE 0.225 A, 300 V, 2 ELEMENT, SILICON, SIGNAL DIODE, TO-236AB, ROHS COMPLIANT, PLASTIC PACKAGE-3, Signal Diode |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS9092ACNTE3 | 制造商:Semtech Corporation 功能描述:270Mb/s Transmitter for SDI & ASI |
| GS9092CNE3 | 制造商:Gennum Corporation 功能描述: |
| GS9092-CNE3 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS90A12-P1M | 功能描述:插入式交流適配器 80W 12V 6.67A RoHS:否 制造商:Phihong 地區:Universal 安裝風格:Wall, Interchangeable Plug 輸入電壓范圍:90 VAC to 264 VAC 輸出端數量:1 輸出功率額定值:5 W 輸出電壓（通道 1）:5 V 輸出電流（通道 1）:1 A 直流輸出連接器:USB Type A 隨附/必需的交流插頭:Required 商用/醫用:Commercial 效率:Level V |
| GS90A15-P1M | 功能描述:插入式交流適配器 90W 15V 6A RoHS:否 制造商:Phihong 地區:Universal 安裝風格:Wall, Interchangeable Plug 輸入電壓范圍:90 VAC to 264 VAC 輸出端數量:1 輸出功率額定值:5 W 輸出電壓（通道 1）:5 V 輸出電流（通道 1）:1 A 直流輸出連接器:USB Type A 隨附/必需的交流插頭:Required 商用/醫用:Commercial 效率:Level V |
發布緊急采購，3分鐘左右您將得到回復。