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參數資料
| 型號： | HMS81C43XX |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER FOR TELEVISION |
| 中文描述： | CMOS單芯片8位單片機電視 |
| 文件頁數： | 35/100頁 |
| 文件大小： | 1943K |
| 代理商： | HMS81C43XX |
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HMS81C43xx / GMS87C4060
35
November 2001 ver 1.2
11. TIMER
11.1 Basic Interval Timer
The HMS81C43xx/GMS87C4060 has one 8-bit Basic In-
terval Timer that is free-run and can not be stopped. Block
diagram is shown in Figure 11-1 .
The Basic Interval Timer generates the time base for
watchdog timer counting, and etc. It also provides a Basic
interval timer interrupt (BITIF). As the count overflow
from FF
H
to 00
H
, this overflow causes the interrupt to be
generated. The Basic Interval Timer is controlled by the
clock control register (CKCTLR) shown in Figure 11-2 .
Source clock can be selected by lower 3 bits of CKCTLR.
BITR and CKCTLR are located at same address, and ad-
dress 00D6
H
is read as a BITR and written to CKCTLR..
Figure 11-1 Block Diagram of Basic Interval Timer
Table 11-1 Basic Interval Timer Interrupt Time
MUX
Basic Interval Timer Interrupt
BITR
Select Input clock
3
source
clock
8-bit up-counter
BITCK
BTCL
f
ex
÷
2
10
f
ex
÷
2
11
f
ex
÷
2
9
f
ex
÷
2
8
f
ex
÷
2
7
f
ex
÷
2
6
f
ex
÷
2
5
f
ex
÷
2
4
Watchdog timer clock (WDTCK)
clear
overflow
Internal bus line
[0D6
H
]
CKCTLR
[0D6
H
]
BITIF
Clock control register
ON
BTS2 BTS1
BTS0
PS4
PS5
PS6
PS7
PS8
PS9
PS10
PS11
BTS2~0
Source clock
Interrupt
(overflow) Period
Pre-Scaler output
At f
ex
=8MHz
000
001
010
011
100
101
110
111
PS4
PS5
PS6
PS7
PS8
PS9
PS10
PS11
f
ex
÷
2
4
f
ex
÷
2
5
f
ex
÷
2
6
f
ex
÷
2
7
f
ex
÷
2
8
f
ex
÷
2
9
f
ex
÷
2
10
f
ex
÷
2
11
0.512
1.024
2.048
4.096
8.192
16.384
32.768
65.536
mS
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相關代理商/技術參數 |
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| HMS81C4460 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS |
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| HMS87C1102A | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:8-BIT SINGLE-CHIP MICROCONTROLLERS |
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