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參數資料
| 型號： | HMS81C43XX |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER FOR TELEVISION |
| 中文描述： | CMOS單芯片8位單片機電視 |
| 文件頁數： | 36/100頁 |
| 文件大小： | 1943K |
| 代理商： | HMS81C43XX |
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HMS81C43xx / GMS87C4060
36
November 2001 ver 1.2
Figure 11-2 BITR: Basic Interval Timer Mode Register
11.2 Timer 0, 1
Timer 0, 1 consists of prescaler, multiplexer, 8-bit compare
data register, 8-bit count register, Control register, and
Comparator as shown in Figure 11-3 .
These Timers can run separated 8bit timer or combined
16bit timer. These timers are operated by internal clock.
The contents of TDR1 are compared with the contents of
up-counter T1. If a match is found, a timer/counter 1 inter-
rupt (T1IF) is generated, and the counter is cleared. Count-
ing up is resumed after the counter is cleared.
Note:
You can read Timer 0, Timer 1 value from TDR0 or
TDR1. But if you write data to TDR0 or TDR1, it changes
Timer 0 or Timer 1 modulo data, not Timer value.
The content of TDR0, TDR1 must be initialized (by soft-
ware) with the value between 01
H
and FF
H
,not to 00
H
.
Or not, Timer 0 or Timer 1 can not count up forever.
The control registers for Timer 0,1 are shown below.
CKCTLR
INITIAL VALUE: Undefined
ADDRESS: 00D6
H
BITR
Both register are in same address,
when write, to be a CKCTLR,
when read, to be a BITR.
Caution
:
8-BIT BINARY COUNTER
ADDRESS : 00D6
H
RESET VALUE : --01 0111
b
ON
BTS2
BTS1
BTS0
Peri. Clock
0: Stop
1: Supply
Watch-dog
timer select
0: Normal 6bit timer
1: Watch-dog timer
B.I.T set
0: Free run
1: Clear 8-bit counter (BITR) to "0". This bit becomes 0
automatically after 1 machine cycle
B.I.T Clock
W
W
W
W
W
W
R
R
R
R
R
R
R
R
Timer mode register 0
TM0
ADDRESS : 00D0
RESET VALUE : -000 0000
b
RW
RW
RW
Timer 0 data register
TDR0
ADDRESS : 00D2
RESET VALUE : Undefined
RW
RW
RW
T1SL0 T0ST
T0CN T0SL1 T0SL0
T1SL1
T1ST
Timer 1 data register
TDR1
ADDRESS : 00D3
RESET VALUE : Undefined
RW
RW
RW
Timer 0 input clock
00: PS2 (f
ex
/ 2
2
)
01: PS4 (f
ex
/ 2
4
)
10: PS6 (f
ex
/ 2
6
)
11: PS8 (f
ex
/ 2
8
)
Timer 1 input clock
00: Timer 0 overflow (16bit mode)
01: PS2 (f
ex
/ 2
2
)
10: PS4 (f
ex
/ 2
4
)
11: PS6 (f
ex
/ 2
6
)
0: Count Hold
1: Count Continue
Timer 0 control
0: Count Hold
1: Count Clear and Start
Timer 0 start
0: Count Hold
1: Count Clear and Start
Timer 1 start
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
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