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參數資料
| 型號： | HMS81C43XX |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER FOR TELEVISION |
| 中文描述： | CMOS單芯片8位單片機電視 |
| 文件頁數： | 48/100頁 |
| 文件大小： | 1943K |
| 代理商： | HMS81C43XX |
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HMS81C43xx / GMS87C4060
48
November 2001 ver 1.2
8bit PWM Control
The HMS81C43xx/GMS87C4060 contains a one 14bit
PWM and six 8bit PWM module.
1. 8bit PWM0~5 is wholy same internal circuit, but
PWM0~5 output port is NMOS open drain.
2. Al l PWM polarity has the same by POL2’s value.
3. Calulate Frame cycle and Pulse width is as following.
PWM Frame Cycle = 2
13
/ f
ex
(Sec)
PWM Width = (PWMRn+1) * 2
5
/ f
ex
(n=0~5)
Pulse Duty (%) = (PWMRn +1) / 256 *100(%) (n=0~5)
Figure 14-3 Wave form example for 8bit PWM
4. PWM output is enabled during ENn(n=0~5) bit (See
PWMCR1~2) contains 1.
Figure 14-4 8bit PWM Registers
5. CNTB controls all PWM counter enable.
If CNTB=0, Counter is enabled.
14bit PWM Control
1. 14bit PWM’s operation concept is not the same as 8bit
PWM.
1 PWM frame contains 64 sub PWMs.
PWM8H : Set sub PWM’s basic Pulse Width.
PWM8L : Number of sub PWM which is added 1 clock.
2. PWM polarity is selected by POL1’s value.
If POL1=0, Positive Polarity.
3. Calulate Frame cycle and Pulse width is as following.
Main PWM Frame Cycle = 2
16
/ f
ex
(Sec).
Sub PWM Frame Cycle = Main Frame Cycle / 64.
4. Table 14-1, “PWM8L and Sub frame matching table,”
on page 48 show PWM8L function.
Figure 14-5 Wave form example for 14bit PWM
Positive Polarity (POL2=0)
1
2
Negative Polarity (POL2=1)
1
2
1. Frame cycle
2. Pulse Width
PWM Data Register
PWMR0~5
ADDRESS : 0E0~E5
RESET VALUE : Undefined
W
W
W
D7
D6
D5
D4
D3
D2
D1
D0
EN5,4,3,2,1 : R47,45,43,42,41,40
0: R4x acts normal digital port
1: R4x acts PWM output port
PWM control Register 1
PWMCR1
ADDRESS : 0EA
RESET VALUE : 0000 0000
b
RW
RW
RW
EN2
EN1
EN0
EN8
CNTB
EN3
EN4
EN5
PWM control Register 2
PWMCR2
ADDRESS : 0EB
RESET VALUE : --0- 00--
b
RW
POL2 POL1
BUZS
8bit PWM Polarity
0: Positive (PWM from Rising edge)
1: Negative (PWM from Rising edge)
14bit Counter enable
0: Counter run
1: Counter stop
W
W
W
W
W
RW
RW
RW
RW
RW
RW
RW
Bit value
Sub frame number which is
added 1 clock
Pulse
count
if Bit0=1
32
1
if Bit1=1
16, 48
2
if Bit2=1
8, 24, 40, 56
4
if Bit3=1
4, 12, 20, 28, 36, 44, 52, 60
8
if Bit4=1
2, 6, 10, 14, 18, 22, 26, 30, 34,
38, 42, 46, 50, 54
16
if Bit5=1
1, 3, 5, 7, 9, 11, 13, 15, 17, 19,
21, 23, 25, 27, 29, 31, 33, 35, 37,
39, 41, 43, 45, 47, 49, 51, 53, 55,
57, 59, 61, 63
32
Table 14-1 PWM8L and Sub frame matching table
Main PWM Frame
.....
0
1 2
61 62 63
Sub PWM Frame
Sub PWM Frame
which is added
1 clock
1 clock width : PS2
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