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參數資料
| 型號： | HMS81C43XX |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER FOR TELEVISION |
| 中文描述： | CMOS單芯片8位單片機電視 |
| 文件頁數： | 57/100頁 |
| 文件大小： | 1943K |
| 代理商： | HMS81C43XX |
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HMS81C43xx / GMS87C4060
57
November 2001 ver 1.2
and right side of character.
bit 7: DUSPCL
It controls sprite’s dot clock and scan line speed. It does not
affect to OSD. Sprite size is controlled as below.
Figure 17-4 OSD Registers - 2
OSDPOL
bit7~0 : POL HS, VS, I, YM, YS, B, G, R
It controls HS, VS, I, YM, YS, B, G, R port’s polarity. If
its value is 1, polarity is active high.
FDWSET
FDWSET (Field Detection Window Seting) register de-
tects the begin of VSync(Vertical Sync.) signal and distin-
guishs its current field is Even field or Odd field.
Figure 17-5 FDWSET detection region
The region of FMIN[2:0] ~ FMAX[3:0] is field detection
window.
FMAX[3:0] can divide the region between HSync(Hori-
zontal Sync.) by 16. You can assume there is 4 bit horizon-
tal counter, for example HCOUNT[3:0] which count 0~15.
If the start of VSync is detected at the window, next field
is even. Else if VSync is detected another region of the
window, next field is odd.
It means start of VSync is detected during FMIN[2:0] <
HCOUNT[3:0] < FMAX[3:0] and FPOL value is 0, it dis-
tinguish odd field.
And, start of VSync is detected during FMIN[2:0] <
HCOUNT[3:0] < FMAX[3:0] and FPOL value is 1, it dis-
tinguish even field.
FMIN[2:0], FMAX[3:0] are compared with the horizontal
counter in OSD block.
DUSPCL
DUSP
Size
0
0
Normal
12x16
0
1
x 2
24x32
1
0
Not used
-
1
1
x 4
48x64
Table 17-2 Sprite pattern size
I/O Polarity ( initial ) Register
OSDPOL
ADDRESS : 0AE2
RESET VALUE : Undefined
W
W
W
POL
VS
POLI
POL
YM
POL
YS
POLB POLG POLR
POL
HS
0: Active Low
1: Active High
OSD display enable,
include the edge color.
0: Off
1: On
POLHS
POLVS
POLI
POLYM
POLB
POLG
POLR
: Hsync. input
: Vsync. input
: Half intensity output
: Half blank output
: Blue output
: Green output
: Red output
Field detection Register
FDWSET
ADDRESS : 0AE3
RESET VALUE : 0111 1010
b
W
W
W
FPOL
FMIN2 ~ 0
FM AX3 ~ 0
Field detection polarity
0: Detect Odd field
Masking range : Min.~Max.
1: Detect Even field
Detecting range : Min.~Max.
Field detection
Maximum pointer
Field detection
Minimum pointer
W
W
W
W
W
W
W
W
W
W
HSync
Ex1: VSync(Odd)
Ex2: VSync(Even)
FMIN
FMAX
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