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參數資料
| 型號： | HSP50110JI-52 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 通信及網絡 |
| 英文描述： | Digital Quadrature Tuner |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQCC84 |
| 文件頁數： | 11/24頁 |
| 文件大小： | 199K |
| 代理商： | HSP50110JI-52 |
3-239
The calculation of the decimation factor depends on whether
the output sample rate is fixed or adjusted dynamically. For a
fixed sample rate, the decimation factor is equal to the divisor
loaded into the programmable divider. For example, if the
divider is configured with a divisor of 8, the decimation factor
is 8 (i.e., the output data rate is F
s
/8). If the decimation factor
is adjusted dynamically, it is a function of both the
programmable divisor and the frequency of carry outs from
the Re-Sampler NCO (F
CO
) as given by:
Decimation Factor =
(Programmable Divisor) x F
s
/F
CO
For example, if the programmable divisor is 8 and F
s
/F
CO
=
40, the decimation factor would be 320.
(EQ. 10)
NOTE: The CIC filter architecture only supports
decimation factors up to 4096.
The phase accumulator in the Re-Sampler NCO generates
the carry outs used to clock the programmable divider. The
frequency at which carry outs are generated (F
CO
) is
determined by the values loaded into the Sampler Center
Frequency (SCF) and Sampler Offset Frequency (SOF)
Registers. The relationship between the values loaded into
these registers and the frequency of the carry outs is given by:
F
CO
= F
s
x (SCF + SOF)/2
32
where F
s
is the input sample rate of the Low Pass Filter
Section, SCF is the 32-bit value loaded into the Sampler
(EQ. 11)
Center Frequency Register, and SOF is the 32-bit value
loaded into the Sample Offset Frequency Register. The SCF
Register is loaded through the Microprocessor Interface (see
Microprocessor Interface Section), and the SOF Register is
loaded serially via the SOF and SOFSYNC inputs (see Serial
Input Section). The sample rate F
s
is a function of the Input
Controller Mode. If the Controller is in Gated Input Mode, F
s
is
the frequency with which ENI is asserted. In Interpolated Input
Mode, F
s
is the CLK frequency (see Input Controller Section).
The carry out and 5 of the most significant 8 bits of the
NCO’s phase accumulator are output to control a resampling
filter such as the HSP43168. The resampling filter can be
used to provide finer time (symbol phase) resolution than
can be achieved by the sampling clock alone. This may be
needed to improve transmit/receive timing or better, align a
matched filter’s impulse response with the symbol
boundaries of a baseband waveform at high symbol rates.
The carry out of the NCO’s phase accumulator is output on
SSTRB, and a window of 5 of the 8 most significant 8 bits of
the Phase Accumulator are output on SPH0-4.
Output Formatter
The Output Formatter supports either Word Parallel or Bit
Serial output modes. The output can be chosen to have a
two’s complement or offset binary format. The configuration
is selected by loading the I/O Formatting/Control Register
(see Table 10).
In parallel output mode, the in-phase and quadrature
samples are output simultaneously at rates up to the
maximum CLK. The DATARDY output is asserted on the first
CLK cycle that new data is available on IOUT0-9 and
QOUT0-9 as shown in Figure 14. Output enables (OEI,
OEQ) are provided to individually three-state IOUT0-9 and
QOUT0-9 for output multiplexing.
When bit serial output is chosen, two serial output modes are
provided, Simultaneous I/Q Mode and I Followed by Q Mode.
In Simultaneous I/Q Mode, the 10-bit I and Q samples are
output simultaneously on IOUT0 and QOUT0 as shown in
Figure 15. In I Followed by Q Mode, both samples are output
on IOUT0 with I samples followed by Q samples as shown in
Figure 16. In this mode, the I and Q samples are packed into
separate 16-bit serial words (10 data bits + 6 zero bits). The
10 data bits are the 10 MSBs of the serial word, and the I
sample is differentiated from the Q sample by a 1 in the LSB
position of the 16-bit data word. A continuous serial output
clock is provided on IOUT9 which is derived by dividing the
SHIFT REG
REG
SOF
SOFSYNC
32
32
0
SOF ENABLE
0
LOAD
RESAMPLER
SAMPLER
CENTER
FREQUENCY
32-BIT ADDER
CARRY OUTPUT
SPH0-4
SHIFTER
5
32
MODE
SSTRB
LOAD
ON CF
WRITE
SOF
SCF
RE-SAMPLER
NCO
PROGRAMMABLE
DIVIDER
TO DECIMATING FILTERS
REG
REG
REG
REG
MUX
SYNC
SYNC
MUX
+
Controlled via microprocessor interface.
FIGURE 13. RE-SAMPLER
MUX
CLK
SAMPLE PHASE
OUT CONTROL
SYNC
DATARDY
8
NCO
CLK
DATARDY
IOUT9-0/
QOUT9-0
NOTE:
DATARDY may be programmed active high or low.
FIGURE 14. PARALLEL OUTPUT TIMING
HSP50110
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相關代理商/技術參數 |
參數描述 |
|---|---|
| HSP50110JI-52Z | 制造商:Intersil Corporation 功能描述:PB-FREE W/ANNEAL DIGITAL QUADRATURE TUNER 84 PLCC,52MHZ,INDU - Rail/Tube |
| HSP50210 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital Costas Loop |
| HSP50210JC-52 | 功能描述:上下轉換器 COSTAS DEMODULATOR,84 PLCC,52MHZ,COMM RoHS:否 制造商:Texas Instruments 產品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50210JC-52Z | 功能描述:上下轉換器 COSTAS DEMODULATOR 84 PLCC 52MHZ COM RoHS:否 制造商:Texas Instruments 產品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50210JI-52 | 功能描述:上下轉換器 COSTAS DEMODULATOR,84 PLCC,52MHZ,IND RoHS:否 制造商:Texas Instruments 產品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
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