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參數資料
| 型號： | HSP50110JI-52 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 通信及網絡 |
| 英文描述： | Digital Quadrature Tuner |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQCC84 |
| 文件頁數： | 14/24頁 |
| 文件大小： | 199K |
| 代理商： | HSP50110JI-52 |
3-242
Thus, the minimum input signal will be -21.66dB below full
scale (-9.66 -12 for A/D Backoff). As before the maximum
input signal in the absence of noise is -12dB down due to
A/D backoff.
From Equation 14, the gain relationships for maximum and
minimum input can be written as follows:
Min Input Level
-6.02dB
≥
-21.66 -6.02 - 216.74 + G
AGC
+ G
SHIFTER
+
20*log((40 x 10
6
/32 x 10
3
)
3
)-2.27
Max Input Level
-6.02dB
≤
-12 - 6.02 - 216.74 + G
AGC
+ G
SHIFTER
+
20 x log((40 x 10
6
/32 x 10
3
)
3
) -2.27
Using the upper and lower limits found above, the gain range
can be expressed as,
45.20dB < G
AGC
+ G
SHIFTER
< 54.86dB.
Using Equation 2 in the previous example, the shifter gain is
determined to be 2
7
, resulting in an AGC gain range of 3.05dB
< G
AGC
<12.72dB.
(EQ. 21)
(EQ. 22)
(EQ. 23)
(EQ. 24)
Basic Architectural Configurations
Detailed architectural diagrams are presented in Figures 18
through 20 for the basic configurations, Integrate/Dump filtering
with optional compensation, 3rd Order CIC filtering with
optionalcompensation,andDecimatingFilterbypass.Onlyone
of the data paths is shown since the processing on either the
inphase or quadrature legs is identical. These diagrams are
useful for determining the throughput pipeline delay or the loop
delay of the AGC as all the internal registers are shown.
All registers with the exception of those denoted by daggers (
)
are enabled every CLK rate to minimize pipeline latency. The
registers marked by daggers are enabled at the output sample
rate as required by the filtering operation performed. The Loop
Filter accumulator in the AGC is enabled once per output
sample, and represents a delay of one output sample. The
accumulators in the CIC filter each represent a delay of one
CLK, but they are enabled for processing once per input
sample. In Interpolated Input Mode the accumulators are
enabled every CLK since the sample rate is determined by the
CLK rate (see Input Controller Section). In Gated Input Mode,
the processing delay of the accumulators is one CLK but they
are only enabled once for each sample gated into the
processing pipeline. As a result, the latency through the
accumulators is 3 CLKs rather than 3 input sample periods
when configured as a 3rd order CIC filter.
HSP50110
相關PDF資料 |
PDF描述 |
|---|---|
| HSP50110JC-52 | CONN HEADER HM 2MM 100POS |
| HSP50110 | Digital Quadrature Tuner(數字調諧器) |
| HSP50210 | Digital Costas Loop(數字Costas鎖相環) |
| HSP50214VC | Programmable Downconverter |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| HSP50110JI-52Z | 制造商:Intersil Corporation 功能描述:PB-FREE W/ANNEAL DIGITAL QUADRATURE TUNER 84 PLCC,52MHZ,INDU - Rail/Tube |
| HSP50210 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital Costas Loop |
| HSP50210JC-52 | 功能描述:上下轉換器 COSTAS DEMODULATOR,84 PLCC,52MHZ,COMM RoHS:否 制造商:Texas Instruments 產品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50210JC-52Z | 功能描述:上下轉換器 COSTAS DEMODULATOR 84 PLCC 52MHZ COM RoHS:否 制造商:Texas Instruments 產品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50210JI-52 | 功能描述:上下轉換器 COSTAS DEMODULATOR,84 PLCC,52MHZ,IND RoHS:否 制造商:Texas Instruments 產品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
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