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參數資料
| 型號： | HSP50110JI-52 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 通信及網絡 |
| 英文描述： | Digital Quadrature Tuner |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQCC84 |
| 文件頁數： | 2/24頁 |
| 文件大小： | 199K |
| 代理商： | HSP50110JI-52 |
3-230
Pinout
HSP50110 (PLCC)
TOP VIEW
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
I
I
I
G
I
I
I
O
L
S
S
S
S
V
C
S
S
H
I
I
I
I
G
S
S
C
C
C
C
V
C
C
C
C
C
C
C
A
A
G
A
R
W
C
IIN5
IIN4
IIN3
IIN2
GND
IIN1
IIN0
ENI
QIN9
QIN8
QIN7
QIN6
QIN5
QIN4
V
CC
QIN3
QIN2
QIN1
QIN0
PH1
PH0
IOUT1
IOUT0
DATARDY
V
CC
CLK
GND
QOUT9
QOUT8
QOUT7
QOUT6
QOUT5
GND
QOUT4
QOUT3
IOUT3
IOUT2
QOUT2
QOUT1
QOUT0
OEQ
V
CC
Pin Description
NAME
TYPE
DESCRIPTION
V
CC
-
+5V Power Supply.
GND
-
Ground.
IIN9-0
I
In-Phase Input. Data input for in-phase (real) samples. Format may be either two’s complement or offset binary format
(see I/O Formatting/Control Register in Table 10). IIN9 is the MSB.
QIN9-0
I
Quadrature Input. Data input for quadrature (imaginary) samples. Format may be either two’s complement or offset bi-
nary format (see I/O Formatting/Control Register in Table 10). QIN9 is the MSB.
ENI
I
Input Enable. When ENI is active ‘low’, data on IIN9-0 and QIN9-0 is clocked into the processing pipeline by the rising
edge of CLK. This input also controls the internal data processing as described in the Input Controller Section of the
data sheet. ENI is active ‘low’.
PH1-0
I
Carrier Phase Offset. The phase of the internally generated carrier frequency may be shifted by 0, 90, 180, or 270 de-
grees by controlling these pins (see Synthesizer/Mixer Section). The phase mapping for these inputs is given in Table 1.
CFLD
I
Carrier Frequency Load. This input loads the Carrier Frequency Register in the Synthesizer NCO (see
Synthesizer/Mixer Section). When this input is sampled ‘high’ by clock, the contents of the Microprocessor Interface
Holding Registers are transferred to the carrier frequency register in the Synthesizer NCO (see Microprocessor Inter-
face Section).
NOTE: This pin must be ‘low’ when loading other configuration data via the Microprocessor In-
terface. Active high Input.
COF
I
Carrier Offset Frequency Input. This serial input is used to load the Carrier Offset Frequency into the Synthesizer NCO
(see Serial Interface Section). The new offset frequency is shifted in MSB first by CLK starting with the clock cycle after
the assertion of COFSYNC.
COFSYNC
I
Carrier Offset Frequency Sync. This signal is asserted one CLK cycle before the MSB of the offset frequency data word
(see Serial Interface Section).
HSP50110
相關PDF資料 |
PDF描述 |
|---|---|
| HSP50110JC-52 | CONN HEADER HM 2MM 100POS |
| HSP50110 | Digital Quadrature Tuner(數字調諧器) |
| HSP50210 | Digital Costas Loop(數字Costas鎖相環) |
| HSP50214VC | Programmable Downconverter |
| HSP50214VI | Programmable Downconverter |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HSP50110JI-52Z | 制造商:Intersil Corporation 功能描述:PB-FREE W/ANNEAL DIGITAL QUADRATURE TUNER 84 PLCC,52MHZ,INDU - Rail/Tube |
| HSP50210 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital Costas Loop |
| HSP50210JC-52 | 功能描述:上下轉換器 COSTAS DEMODULATOR,84 PLCC,52MHZ,COMM RoHS:否 制造商:Texas Instruments 產品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50210JC-52Z | 功能描述:上下轉換器 COSTAS DEMODULATOR 84 PLCC 52MHZ COM RoHS:否 制造商:Texas Instruments 產品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50210JI-52 | 功能描述:上下轉換器 COSTAS DEMODULATOR,84 PLCC,52MHZ,IND RoHS:否 制造商:Texas Instruments 產品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
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