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參數(shù)資料
| 型號： | HSP50110JI-52 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Digital Quadrature Tuner |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQCC84 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大小： | 199K |
| 代理商： | HSP50110JI-52 |
3-235
The Loop Filter Accumulator uses a pseudo floating point
format to provide up to ~48dB of gain correction. The format
of the accumulator output is shown in Figure 3. The AGC
gain is given by:
Gain
AGC
= (1.0 + M) x 2
E
(EQ. 7)
where M is the 4-bit mantissa value ranging from 0.0 to
0.9375, and E is the three bit exponent ranging from 0 to 7.
The result is a piece wise linear transfer function whose
overall response is logarithmic, as shown in Figure 5. The
exponent bits provide a coarse gain setting of 2
(EEE)
. This
corresponds to a gain range from 0dB to 42dB (2
0
to 2
7
) with
the MSB representing a 24dB gain, the next bit a 12dB gain,
and the final bit a 6dB gain. The four mantissa bits map to an
additional gain of 1.0 to 1.9375 (0 to ~6dB). Together, the
exponent and the mantissa portion of the limit set a gain
range from 0 to ~48dB.
The limiter restricts the AGC gain range by keeping the
accumulator output between the programmed limits. If the
accumulator exceeds the upper or lower limit, then the
accumulator is held to that limit. The limits are programmed
via eight bit words which express the values of the upper and
lower limits as eight bit pseudo floating point numbers as
shown in Figure 3 (see AGC Control Register, Table 9). The
format for the limits is the same as the format of the eight
most significant bits of the Loop Filter Accumulator.
Examples of how to set the limits for a specific output signal
level are provided in the “Setting DQT Gains” Section below.
NOTE: A fixed AGC gain may be set by programming
the upper and lower limits to the same value.
The response time of the AGC is determined by the
Programmable Loop Gain. The Loop Gain is an unsigned
8-bit value whose significance relative to the AGC gain is
shown in Figure 3. The loop gain is added or subtracted from
the accumulator depending on the output of the Level
Detector. The accumulator is updated at the output sample
rate. If the accumulator exceeds the upper or lower limit, the
accumulator is loaded with that limit. The slew rate of the
AGC ranges between ~0.001dB and 0.266dB per output
sample for Loop Gains between 01(HEX) and FF (HEX)
respectively.
The user should exercise care when using maximum loop
gain when the (x/sin(x)) or the (x/sin(x))
3
compensation filter is
enabled. At high decimation rates, the delay through the
compensation filter may be large enough to induce
oscillations in the AGC loop. The Basic Architectural
Configurations Section contains the necessary detailed block
diagrams to determine the loop delay for different matched
filter configurations.
Low Pass Filtering
The gain corrected signal feeds a Low Pass Filtering Section
comprised of a Cascaded Integrator Comb (CIC) and
compensation filter. The filtering section extracts the channel
of interest while providing decimation to match the output
sample rate to the channel bandwidth. A variety of filtering
configurations are possible which include integrate and
dump, integrate and dump with x/sin(x) compensation, third
order CIC, and third order CIC with ((x)/sin(x))3
compensation. If none of these filtering options are desired,
the entire filtering section may be bypassed.
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
2
-8
2
-9
2
-10
2
-11
2
-12
2
-13
M
M
M
M
X
G G
EXPONENT
0 TO 7
MANTISSA
0.0 to 0.9375
PROGRAMMABLE
LOOP GAIN
MAPS TO
μ
P AGC
MAPS TO AGC
UPPER AND LOWER LIMITS
2
2
E
2
1
E
2
0
E
L
G
G
G
G
G
G
L
L
L
L
L
L
L
.
FIGURE 3. BINARY FORMAT FOR LOOP FILTER
ACCUMULATOR
LOOP FILTER ACCUMULATOR PARAMETER
This Value Can Be Read By The Microprocessor.
See The Microprocessor Interface Section.
AGC THRESHOLD
LEVEL
DETECTOR
PROGRAMMABLE
LOOP GAIN
UPPER
GAIN
LIMIT
LOWER
GAIN
LIMIT
AGC LOOP FILTER
I DATA
Q DATA
A
REG
+
REG
LIMIT
Indicates data downloaded via microprocessor interface.
FIGURE 4. AGC BLOCK DIAGRAM
AGC L.D. SENSE
AGC
DISABLE
G
G
GAIN CONTROL WORD
(8 MSBs OF LOOP FILTER ACCUMULATOR)
dB
LINEAR
256
240
224
208
192
176
160
144
128
112
96
80
64
48
32
16
0
240
224
208
192
176
160
144
128
112
96
80
64
48
32
16
0
48
42
36
30
24
18
12
6
0
FIGURE 5. GAIN CONTROL TRANSFER FUNCTION
HSP50110
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PDF描述 |
|---|---|
| HSP50110JC-52 | CONN HEADER HM 2MM 100POS |
| HSP50110 | Digital Quadrature Tuner(數(shù)字調(diào)諧器) |
| HSP50210 | Digital Costas Loop(數(shù)字Costas鎖相環(huán)) |
| HSP50214VC | Programmable Downconverter |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50110JI-52Z | 制造商:Intersil Corporation 功能描述:PB-FREE W/ANNEAL DIGITAL QUADRATURE TUNER 84 PLCC,52MHZ,INDU - Rail/Tube |
| HSP50210 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital Costas Loop |
| HSP50210JC-52 | 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR,84 PLCC,52MHZ,COMM RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50210JC-52Z | 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR 84 PLCC 52MHZ COM RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50210JI-52 | 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR,84 PLCC,52MHZ,IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
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