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參數資料
| 型號： | IS42LS81600A-7TI |
| 英文描述： | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| 中文描述： | 16Meg × 8，8Meg x16 |
| 文件頁數： | 8/66頁 |
| 文件大小： | 556K |
| 代理商： | IS42LS81600A-7TI |
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ISSI
8
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
ADVANCED INFORMATION
Rev. 00A
06/01/02
IS42S81600A, IS42S16800A, IS42S32400A
IS42LS81600A, IS42LS16800A, IS42LS32400A
PIN FUNCTIONS
Symbol
Type
Function (In Detail)
A0-A11
Input Pin
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (A0-A7
with A10 defining auto precharge) to select one location out of the memory array
in the respective bank. A10 is sampled during a PRECHARGE command to determine if
all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE
REGISTER command.
BA0, BA1
Input Pin
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
CAS
Input Pin
CAS
, in conjunction with the
RAS
and
WE
, forms the device command. See the
"Command Truth Table" for details on device commands.
CKE
Input Pin
The CKE input determines whether the CLK input is enabled. The next rising edge of the
CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW,
the device will be in either power-down mode, clock suspend mode, or self refresh
mode.
CKE is an
asynchronous i
nput.
CLK
Input Pin
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
CS
Input Pin
The
CS
input determines whether command input is enabled within the device.
Command input is enabled when
CS
is LOW, and disabled with
CS
is HIGH. The device
remains in the previous state when
CS
is HIGH.
I/O0 to
I/O32
I/O Pin
I/O0 to I/O32 are I/O pins. I/O through these pins can be controlled in byte units
using the LDQM and UDQM pins.
LDQM,
UDQM
Input Pin
LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the
corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the
HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to
OE
in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer.
When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can
be written to the device. When LDQM or UDQM is HIGH, input data is masked and
cannot be written to the device.
DQM0-DQM3
Input Pin
DQM
Input Pin
RAS
Input Pin
RAS
, in conjunction with
CAS
and
WE
, forms the device command. See the "Command
Truth Table" item for details on device commands.
WE
Input Pin
WE
, in conjunction with
RAS
and
CAS
, forms the device command. See the "Command
Truth Table" item for details on device commands.
V
DDQ
Power Supply Pin
V
DDQ
is the output buffer power supply.
V
DD
Power Supply Pin
V
DD
is the device internal power supply.
V
SSQ
Power Supply Pin
V
SSQ
is the output buffer ground.
V
SS
Power Supply Pin
V
SS
is the device internal ground.
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