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參數資料
| 型號： | IS42S32400A-10TI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | CABLE ASSEMBLY; BNC MALE TO BNC FEMALE BULKHEAD; 50 OHM, RG174A/U COAX; ; *USES STANDARD 50 OHM INTERFACE CONNECTORS* |
| 中文描述： | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO86 |
| 封裝： | PLASTIC, TSOP2-86 |
| 文件頁數： | 1/66頁 |
| 文件大?。?/td> | 556K |
| 代理商： | IS42S32400A-10TI |
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Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
ADVANCED INFORMATION, Rev. 00A
08/01/02
1
Copyright 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
IS42S81600A, IS42LS81600A
IS42S16800A, IS42LS16800A
IS42S32400A, IS42LS32400A
ISSI
FEATURES
Clock frequency: 133 100, MHz
Fully synchronous; all signals referenced to a
positive clock edge
Internal bank for hiding row access/precharge
Power supply
V
DD
IS42LS81600A
2.5V
IS42LS16800A
2.5V
IS42LS32400A
2.5V
IS42S81600A
3.3V
IS42S16800A
3.3V
IS42S32400A
3.3V
LVTTL interface
Programmable burst length
– (1, 2, 4, 8, full page)
Programmable burst sequence:
Sequential/Interleave
Extended Mode Register
Programmable Power Reduction Feature by
partial array activation during Self-Refresh
Auto Refresh (CBR)
Temp. Compensated Self Refresh.
Self Refresh with programmable refresh periods
4096 refresh cycles every 64 ms
Random column address every clock cycle
Programmable
CAS
latency (2, 3 clocks)
Burst read/write and burst read/single write
operations capability
Burst termination by burst stop and precharge
command
Industrial Temperature Availability
V
DDQ
1.8V (2.5V tolerant)
1.8V (2.5V tolerant)
1.8V (2.5V tolerant)
3.3V
3.3V
3.3V
OVERVIEW
ISSI
's 128Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock
input.The 128Mb SDARM is organized as follows.
16Meg x 8, 8Meg x16 & 4Meg x 32
128-MBIT SYNCHRONOUS DRAM
ADVANCED INFORMATION
AUGUST 2002
KEY TIMING PARAMETERS
Parameter
-7
-10
Unit
Clk Cycle Time
CAS
Latency = 3
CAS
Latency = 2
7
10
10
10
ns
ns
Clk Frequency
CAS
Latency = 3
CAS
Latency = 2
133
100
100
100
Mhz
Mhz
Access Time from Clock
CAS
Latency = 3
CAS
Latency = 2
5.4
6
7
9
ns
ns
Row to Column Delay Time (t
RCD
)
15
18
ns
Row Precharge Tim (t
RP
)
15
18
ns
IS42LS81600A
IS42S81600A
4M x8x4 Banks
IS42LS16800A
IS42S16800A
2M x16x4 Banks
IS42LS32400A
IS42S32400A
2M x16x4 Banks
54pin TSOPII
54ball FBGA
90ball FBGA
54 pin TSOPII
86pin TSOPII
相關PDF資料 |
PDF描述 |
|---|---|
| IS42S32400A-10TL | CABLE ASSEMBLY; SMA MALE RIGHT ANGLE TO; SMA FEMALE BULKHEAD; 50 OHM, PE-SR405FL (.085" RE-SHAPABLE); 18" CABLE LENGTH; |
| IS42S32400A-10TLI | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S16800A | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S16800A-6T | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S16800A-6TL | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| IS42S32400A-10TL | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400A-10TLI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400A-6T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400A-6TL | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS42S32400A-6T-TR | 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 128M-Bit 4Mx32 3.3V 86-Pin TSOP-II T/R |
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