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參數(shù)資料
型號(hào)： IS42S32400A-10TI
廠商： INTEGRATED SILICON SOLUTION INC
元件分類： DRAM
英文描述： CABLE ASSEMBLY; BNC MALE TO BNC FEMALE BULKHEAD; 50 OHM, RG174A/U COAX; ; *USES STANDARD 50 OHM INTERFACE CONNECTORS*
中文描述： 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO86
封裝： PLASTIC, TSOP2-86
文件頁數(shù)： 21/66頁
文件大小： 556K
代理商： IS42S32400A-10TI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
ADVANCED INFORMATION
Rev. 00A
06/01/02
21
ISSI
IS42S81600A, IS42S16800A, IS42S32400A
IS42LS81600A, IS42LS16800A, IS42LS32400A
AC ELECTRICAL CHARACTERISTICS
(1,2,3)
-7
-10
Symbol
Parameter
Min.
Max.
Min.
Max
Units
t
CK3
t
CK2
Clock Cycle Time
CAS
Latency = 3
CAS
Latency = 2
7
—
—
10
10
—
—
ns
ns
10
t
AC3
t
AC2
Access Time From CLK
(4)
CAS
Latency = 3
CAS
Latency = 2
—
—
5.4
6
—
—
7
9
ns
ns
t
CHI
CLK HIGH Level Width
2.5
—
3.5
—
ns
t
CL
CLK LOW Level Width
2.5
—
3.5
—
ns
t
OH3
t
OH2
Output Data Hold Time
CAS
Latency = 3
CAS
Latency = 2
2.5
2.5
—
—
2.5
2.5
—
—
ns
ns
t
LZ
Output LOW Impedance Time
0
—
0
—
ns
t
HZ3
t
HZ2
Output HIGH Impedance Time
(5)
CAS
Latency = 3
—
—
6
6
—
—
7
9
ns
ns
CAS
Latency = 2
t
DS
Input Data Setup Time
1.5
—
2.0
—
ns
t
DH
Input Data Hold Time
0.8
—
1
—
ns
t
AS
Address Setup Time
.5
—
2.0
—
ns
t
AH
Address Hold Time
0.8
—
1
—
ns
t
CKS
CKE Setup Time
1.5
—
2.0
—
ns
t
CKH
CKE Hold Time
0.8
—
1
—
ns
t
CKA
CKE to CLK Recovery Delay Time
1CLK+3
—
1CLK+3
—
ns
t
CS
Command Setup Time (
CS
,
RAS
,
CAS
,
WE
, DQM)
1.5
—
2.0
—
ns
t
CH
Command Hold Time (
CS
,
RAS
,
CAS
,
WE
, DQM)
0.8
—
1
—
ns
t
RC
Command Period (REF to REF / ACT to ACT)
63
—
70
—
ns
t
RAS
Command Period (ACT to PRE)
37
120,000
44
120,000
ns
t
RP
Command Period (PRE to ACT)
15
—
18
—
ns
t
RCD
Active Command To Read / Write Command Delay Time
15
—
18
—
ns
t
RRD
Command Period (ACT [0] to ACT[1])
14
—
15
—
ns
t
DPL3
Input Data To Precharge
Command Delay time
CAS
Latency = 3
2CLK
—
2CLK
—
ns
t
DPL2
CAS
Latency = 2
2CLK
—
2CLK
—
ns
t
DAL3
Input Data To Active / Refresh
CAS
Latency = 3
Command Delay time (During Auto-Precharge)
CLK+t
RP
—
2CLK+t
RP
—
ns
t
DAL2
CAS
Latency = 2
2CLK+t
RP
—
2CLK+t
RP
—
ns
t
T
Transition Time
0.5
30
0.5
30
ns
t
REF
Notes:
1. When power is first applied, memory operation should be started 100 μs after Vdd and Vdd
Q
reach their stipulated voltages.
Also note that the power-on sequence must be executed before starting memory operation.
2. Measured with t
T
= 1 ns.
3. The reference level is 0.9V when measuring input signal timing. Rise and fall times are measured between V
IH
(min.) and V
IL
(max.).
4. Access time is measured at 0.9V with the load shown in the figure below.
5. The time t
HZ
(max.) is defined as the time required for the output voltage to transition by ± 200 mV from V
OH
(min.) or V
OL
(max.)
when the output is in the high impedance state.
Refresh Cycle Time (4096)
—
64
—
64
ms
相關(guān)PDF資料
PDF描述
IS42S32400A-10TL CABLE ASSEMBLY; SMA MALE RIGHT ANGLE TO; SMA FEMALE BULKHEAD; 50 OHM, PE-SR405FL (.085" RE-SHAPABLE); 18" CABLE LENGTH;
IS42S32400A-10TLI 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM
IS42S16800A 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM
IS42S16800A-6T 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM
IS42S16800A-6TL 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IS42S32400A-10TL 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM
IS42S32400A-10TLI 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM
IS42S32400A-6T 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM
IS42S32400A-6TL 制造商:Integrated Silicon Solution Inc 功能描述:
IS42S32400A-6T-TR 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 128M-Bit 4Mx32 3.3V 86-Pin TSOP-II T/R
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