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參數(shù)資料
| 型號： | IS42S32400A-10TI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | CABLE ASSEMBLY; BNC MALE TO BNC FEMALE BULKHEAD; 50 OHM, RG174A/U COAX; ; *USES STANDARD 50 OHM INTERFACE CONNECTORS* |
| 中文描述： | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO86 |
| 封裝： | PLASTIC, TSOP2-86 |
| 文件頁數(shù)： | 29/66頁 |
| 文件大?。?/td> | 556K |
| 代理商： | IS42S32400A-10TI |
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Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
ADVANCED INFORMATION
Rev. 00A
06/01/02
29
ISSI
IS42S81600A, IS42S16800A, IS42S32400A
IS42LS81600A, IS42LS16800A, IS42LS32400A
REGISTER DEFINITION
Mode Register
The mode register is used to define the specific mode of
operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS\ latency, an
operating mode and a write burst mode, as shown in MODE
REGISTER DEFINITION.
The mode register is programmed via the LOAD MODE
REGISTER command and will retain the stored information
until it is programmed again or the device loses power.
Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst
(sequential or interleaved)
, M4- M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and
M11 are reserved for future use.
The mode register must be loaded when all banks are idle,
and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
MODE REGISTER DEFINITION
Latency Mode
M6 M5 M4
0
0
0
0
1
1
1
1
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1. To ensure compatibility with future devices,
should program M11, M10 = "0, 0"
Write Burst Mode
M9
Mode
Programmed Burst Length
Single Location Access
0
1
Operating Mode
M8 M7
0
— —
M6-M0
Defined
—
Mode
Standard Operation
All Other States Reserved
0
Burst Type
M3
Type
0
1
Sequential
Interleaved
Burst Length
M2 M1 M0
0
0
0
0
1
1
1
1
M3=0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3=1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Address Bus
Mode Register (Mx)
A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
(1)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS42S32400A-10TL | CABLE ASSEMBLY; SMA MALE RIGHT ANGLE TO; SMA FEMALE BULKHEAD; 50 OHM, PE-SR405FL (.085" RE-SHAPABLE); 18" CABLE LENGTH; |
| IS42S32400A-10TLI | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S16800A | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S16800A-6T | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S16800A-6TL | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS42S32400A-10TL | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400A-10TLI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400A-6T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400A-6TL | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS42S32400A-6T-TR | 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 128M-Bit 4Mx32 3.3V 86-Pin TSOP-II T/R |
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