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參數(shù)資料
型號: ISP1161ABM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù): 101/134頁
文件大小: 587K
代理商: ISP1161ABM
Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
101 of 134
9397 750 13962
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
13.2.3
Stall Endpoint/Unstall Endpoint (40H–4FH/80H—8FH)
These commands are used to stall or unstall an endpoint. The commands modify the
content of the DcEndpointStatus register (see
Table 92
).
A stalled control endpoint is automatically unstalled when it receives a SETUP token,
regardless of the packet content. If the endpoint should stay in its stalled state, the
microprocessor can re-stall it with the Stall Endpoint command.
When a stalled endpoint is unstalled (either by the Unstall Endpoint command or by
receiving a SETUP token), it is also re-initialized. This flushes the buffer: if it is an
OUT buffer it waits for a DATA 0 PID, if it is an IN buffer it writes a DATA 0 PID.
Code (Hex): 40 to 4F —
stall (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 80 to 8F —
unstall (control OUT, control IN, endpoint 1 to 14)
Transaction —
none
13.2.4
Validate Endpoint Buffer (R/W: 6FH/61H)
This command signals the presence of valid data for transmission to the USB host, by
setting the Buffer Full flag of the selected IN endpoint. This indicates that the data in
the buffer is valid and can be sent to the host, when the next IN token is received. For
a double-buffered endpoint this command switches the current FIFO for CPU access.
Remark:
For special aspects of the control IN endpoint see
Section 11.3.6
.
Code (Hex): 61 to 6F —
validate endpoint buffer (control IN, endpoint 1 to 14)
Transaction —
none
Table 93:
Bit
7
DcEndpointStatus register: bit description
Symbol
Description
EPSTAL
This bit indicates whether the endpoint is stalled or not
(1 = stalled, 0 = not stalled).
Set to logic 1 by a Stall Endpoint command, cleared to logic 0 by
an Unstall Endpoint command. The endpoint is automatically
unstalled upon reception of a SETUP token.
EPFULL1
Logic 1 indicates that the secondary endpoint buffer is full.
EPFULL0
Logic 1 indicates that the primary endpoint buffer is full.
DATA_PID
This bit indicates the data PID of the next packet (0 = DATA PID,
1 = DATA1 PID).
OVERWRITE
This bit is set by hardware, logic 1 indicating that a new Setup
packet has overwritten the previous set-up information, before it
was acknowledged or before the endpoint was stalled. If writing
the set-up data has finished, this bit is cleared by a read action.
Firmware must check this bit before sending an Acknowledge
Setup command or stalling the endpoint. Upon reading logic 1,
the firmware must stop ongoing setup actions and wait for a new
Setup packet.
SETUPT
Logic 1 indicates that the buffer contains a Setup packet.
CPUBUF
This bit indicates which buffer is currently selected for CPU
access (0 = primary buffer, 1 = secondary buffer).
-
reserved
6
5
4
3
2
1
0
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