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參數資料
| 型號： | ISP1561 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | ISP1561BM |
| 中文描述： | ISP1561BM |
| 文件頁數： | 18/102頁 |
| 文件大小： | 2875K |
| 代理商： | ISP1561 |
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Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
18 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Status register (address: 06H):
The Status register is a two-byte read-only register
used to record status information on PCI bus-related events (bit allocation: see
Table 8
).
5
VGAPS
VGA Palette Snoop
: This bit controls how VGA compatible and
graphics devices handle accesses to VGA palette registers. When
this bit is logic 1, palette snooping is enabled (that is, the device
does not respond to palette register writes and snoops the data).
When the bit is logic 0, the device should treat palette write
accesses like all other accesses. VGA compatible devices should
implement this bit.
Memory Write and Invalidate Enable
: This is an enable bit for
using the Memory Write and Invalidate command. When this bit is
logic 1, masters may generate the command. When it is logic 0,
Memory Writes must be used instead. State after RST# is logic 0.
This bit must be implemented by master devices that can generate
the Memory Write and Invalidate command.
Special Cycles
: Controls the action of a device on Special Cycle
operations. A value of logic 0 causes the device to ignore all
Special Cycle operations. A value of logic 1 allows the device to
monitor Special Cycle operations. State after RST# is logic 0.
Bus Master
: Controls the ability of a device to act as a master on
the PCI bus. A value of logic 0 disables the device from generating
PCI accesses. A value of logic 1 allows the device to behave as a
bus master. State after RST# is logic 0.
Memory Space
: Controls the response of a device to Memory
Space accesses. A value of logic 0 disables the device response.
A value of logic 1 allows the device to respond to Memory Space
accesses. State after RST# is logic 0.
IO Space
: Controls the response of a device to I/O Space
accesses. A value of logic 0 disables the device response. A value
of logic 1 allows the device to respond to I/O Space accesses.
State after RST# is logic 0.
4
MWIE
3
SC
2
BM
1
MS
0
IOS
Table 7:
Bit
Command register: bit description
…continued
Symbol
Description
Table 8:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Status register: bit allocation
15
DPE
0
R
7
FBBC
0
R
14
SSE
0
R
6
reserved
0
-
13
RMA
0
R
5
66MC
0
R
12
RTA
0
R
4
CL
1
R
11
STA
0
R
3
10
DEVSELT[1:0]
0
R
2
reserved
0
-
9
8
MDPE
0
R
0
1
R
1
0
-
0
-
0
-
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1561BM | ISP1561BM |
| ISP1562 | Hi-Speed Universal Serial Bus PCI Host Controller |
| ISP1562BE | Hi-Speed Universal Serial Bus PCI Host Controller |
| ISP1581 | Universal Serial Bus 2.0 high-speed interface device |
| ISP1581BD | Universal Serial Bus 2.0 high-speed interface device |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1561 HI-SPEED USB H | 制造商:NXP Semiconductors 功能描述: |
| ISP1561BM | 制造商:NXP Semiconductors 功能描述: |
| ISP1561BM,518 | 功能描述:USB 接口集成電路 USB 2.0 HOST CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1561BM,551 | 功能描述:USB 接口集成電路 USB 2.0 HOST CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1561BM,557 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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