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參數資料
| 型號： | ISP1561 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | ISP1561BM |
| 中文描述： | ISP1561BM |
| 文件頁數： | 78/102頁 |
| 文件大小： | 2875K |
| 代理商： | ISP1561 |
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Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
78 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
11.4.4
FRINDEX register (address: value read from func2 of address 10H + 18H)
The Frame Index (FRINDEX) register is used by the Host Controller to index into the
periodic frame list. The register updates every 125
μ
s (once each microframe).
Bits N to 3 are used to select a particular entry in the Periodic Frame List during
periodic schedule execution. The number of bits used for the index depends on the
size of the frame list as set by system software in the FLS (Frame List Size) field in
the USBCMD register. This register must be written as a DWord. Byte writes produce
undefined results. This register cannot be written unless the Host Controller is in the
Bit
Symbol
Reset
Access
Bit
Symbol
15
14
13
12
11
10
9
8
reserved
0
-
7
0
-
6
0
-
5
0
-
4
0
-
3
0
-
2
0
-
1
0
-
0
reserved
IAAE
HSEE
FLRE
PCIE
USBERR
INTE
0
R/W
USBINTE
Reset
Access
0
-
0
-
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Table 107: USBINTR register: bit description
Bit
Symbol
31 to 6
-
5
IAAE
Description
reserved
Interrupt on Asynchronous Advance Enable
: When this bit is
set and the IAA (Interrupt on Asynchronous Advance) bit in the
USBSTS register is set, the Host Controller issues an interrupt at
the next interrupt threshold. The interrupt is acknowledged by
software clearing the IAA (Interrupt on Asynchronous Advance)
bit.
Host System Error Enable
: When this bit is set and the Host
System Error Status bit in the USBSTS register is set, the Host
Controller issues an interrupt. The interrupt is acknowledged by
software clearing the HSE (Host System Error) bit.
Frame List Rollover Enable
: When this bit is set and the FLR
(Frame List Rollover) bit in the USBSTS register is set, the Host
Controller issues an interrupt. The interrupt is acknowledged by
software clearing the FLR (Frame List Rollover) bit.
Port Change Interrupt Enable
: When this bit is set and the PCD
(Port Change Detect) bit in the USBSTS register is set, the Host
Controller issues an interrupt. The interrupt is acknowledged by
software clearing the PCD (Port Change Detect) bit.
USB Error Interrupt Enable
: When this bit is set and the
USBERRINT bit in the USBSTS register is set, the Host Controller
issues an interrupt at the next interrupt threshold. The interrupt is
acknowledged by software clearing the USBERRINT bit.
USB Interrupt Enable
: When this bit is set and the USBINT bit in
the USBSTS register is set, the Host Controller issues an interrupt
at the next interrupt threshold. The interrupt is acknowledged by
software clearing the USBINT bit.
4
HSEE
3
FLRE
2
PCIE
1
USB
ERRINTE
0
USBINTE
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1561BM | ISP1561BM |
| ISP1562 | Hi-Speed Universal Serial Bus PCI Host Controller |
| ISP1562BE | Hi-Speed Universal Serial Bus PCI Host Controller |
| ISP1581 | Universal Serial Bus 2.0 high-speed interface device |
| ISP1581BD | Universal Serial Bus 2.0 high-speed interface device |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1561 HI-SPEED USB H | 制造商:NXP Semiconductors 功能描述: |
| ISP1561BM | 制造商:NXP Semiconductors 功能描述: |
| ISP1561BM,518 | 功能描述:USB 接口集成電路 USB 2.0 HOST CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1561BM,551 | 功能描述:USB 接口集成電路 USB 2.0 HOST CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1561BM,557 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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