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參數資料
型號: ISP1581BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Universal Serial Bus 2.0 high-speed interface device
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數: 15/73頁
文件大小: 1819K
代理商: ISP1581BD
Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Objective specification
Rev. 02 — 23 October 2000
15 of 73
9397 750 07648
Philips Electronics N.V. 2000. All rights reserved.
9.2.3
Interrupt Configuration register (address: 10H)
This 1-byte register determines the behaviour and polarity of the INT output. The bit
allocation is shown in
Table 9
. When the USB SIE receives or generates a ACK, NAK
or STALL, it will generate interrupts depending on three Debug mode bit fields:
CDBGMOD[1:0]: interrupts for the Control endpoint 0
DDBGMODIN[1:0]: interrupts for the DATA IN endpoints 1 to 7
DDBGMODOUT[1:0]: interrupts for the DATA OUT endpoints 1 to 7.
The Debug mode settings for CDBGMOD, DDBGMODIN and DDBGMODOUT allow
the user to individually configure when the ISP1581 will send an interrupt to the
external microprocessor.
Table 11
lists the available combinations.
Bit INTPOL controls the signal polarity of the INT output (active HIGH or LOW, rising
or falling edge). For level-triggering bit INTLVL must be made logic 0. By setting
INTLVL to logic 1 an interrupt will generate a pulse of 60 ns (edge-triggering).
[1]
First NAK: the first NAK on an IN or OUT token after a previous ACK response.
Table 9:
Bit
Symbol
Reset
Bus reset
Access
Interrupt Configuration register: bit allocation
7
6
CDBGMOD[1:0]
03H
03H
R/W
5
4
3
2
1
0
DDBGMODIN[1:0]
03H
03H
R/W
DDBGMODOUT[1:0]
03H
03H
R/W
INTLVL
0
unchanged
R/W
INTPOL
0
unchanged
R/W
Table 10: Interrupt Configuration register: bit description
Bit
Symbol
7 to 6
CDBGMOD[1:0]
5 to 4
DDBGMODIN[1:0]
3 to 2
DDBGMODOUT[1:0]
1
INTLVL
Description
Control 0 Debug Mode:
values see
Table 11
Data Debug Mode IN:
values see
Table 11
Data Debug Mode OUT:
values see
Table 11
Interrupt Level
: selects the signaling mode on output
INT (0 = level, 1 = pulsed). In pulsed mode an interrupt
produces a 60 ns pulse. Bus reset value: unchanged.
Interrupt Polarity:
selects signal polarity on output INT
(0 = active LOW, 1 = active HIGH). Bus reset value:
unchanged.
0
INTPOL
Table 11: Debug mode settings
Value
CDBGMOD
00H
Interrupt on all ACK,
STALL and NAK
01H
Interrupt on all ACK and
STALL
1XH
Interrupt on all ACK,
STALL and first NAK
[1]
DDBGMODIN
Interrupt on all ACK
and NAK
Interrupt on ACK
DDBGMODOUT
Interrupt on all ACK, STALL,
NYET and NAK
Interrupt on ACK, STALL and
NYET
Interrupt on all ACK, STALL,
NYET and first NAK
[1]
Interrupt on all ACK
and first NAK
[1]
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