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參數資料
| 型號： | ISP1581BD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Universal Serial Bus 2.0 high-speed interface device |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數： | 30/73頁 |
| 文件大小： | 1819K |
| 代理商： | ISP1581BD |
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Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Objective specification
Rev. 02 — 23 October 2000
30 of 73
9397 750 07648
Philips Electronics N.V. 2000. All rights reserved.
[1]
[2]
DREQ is asserted only if space (writing) or data (reading) is available in the FIFO.
This process is stopped when the transfer FIFO becomes empty.
9.4.4
DMA Hardware register (address: 3CH)
The DMA Hardware register consists of 1 byte. The bit allocation is shown in
Table 37
.
This register determines the polarity of the bus control signals (EOT, DACK, DREQ,
DIOR, DIOW) and the DMA mode (master or slave). It also controls whether the
upper and lower parts of the data bus are swapped (bits ENDIAN[1:0]), for modes
GDMA (slave) and MDMA (master) only.
6 to 4
BURST[2:0]
These bits select the DMA burst length and the DREQ timing
(GDMA Slave mode only):
00H —
DREQ is asserted until the last byte/word is
transferred or until the FIFO becomes full or empty
01H —
DREQ is asserted and negated for each byte/word
transferred
[1][2]
02H —
DREQ is asserted and negated for every
2 bytes/words transferred
[1][2]
03H —
DREQ is asserted and negated for every
4 bytes/words transferred
[1][2]
04H —
DREQ is asserted and negated for every
8 bytes/words transferred
[1][2]
05H —
DREQ is asserted and negated for every
12 bytes/words transferred
[1][2]
06H —
DREQ is asserted and negated for every
16 bytes/words transferred
[1][2]
07H —
DREQ is asserted and negated for every
32 bytes/words transferred
[1][2]
.
These bits only affect the GDMA (slave) and MDMA (master)
handshake signals:
00H —
DIOR (master) or DIOW (slave): strobes data from the
DMA bus into the ISP1581; DIOW (master) or DIOR (slave):
puts data from the ISP1581 on the DMA bus
01H —
DIOR (master) or DACK (slave) strobes the data from
the DMA bus into the ISP1581; DACK (master) or DIOR
(slave) puts the data from the ISP1581 on the DMA bus
02H —
DACK (master and slave) strobes the data from the
DMA bus into the ISP1581 and also puts the data from the
ISP1581 on the DMA bus
03H —
reserved.
reserved
This bit selects the DMA bus width for GDMA (slave) and
MDMA (master):
0 —
8-bit data bus
1 —
16-bit data bus.
3 to 2
MODE[1:0]
1
0
-
WIDTH
Table 36: DMA Configuration register: bit description
…continued
Bit
Symbol
Description
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1581BD-S | 功能描述:IC USB CTRL HI-SPEED 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1581BD-T | 功能描述:IC USB CTRL HI-SPEED 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1582 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed Universal Serial Bus peripheral controller |
| ISP1582 PCI EVALKIT | 功能描述:PCI BUS EVAL KIT ISP1582 RoHS:是 類別:編程器，開發系統 >> 評估演示板和套件 系列:- 產品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- 主要目的:電源管理，電池充電器 嵌入式:否 已用 IC / 零件:MAX8903A 主要屬性:1 芯鋰離子電池 次要屬性:狀態 LED 已供物品:板 |
| ISP1582BS | 功能描述:IC USB CTRL HI-SPEED 56HVQFN RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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