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參數資料
| 型號： | LC72133V |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁數： | 11/23頁 |
| 文件大小： | 147K |
| 代理商： | LC72133V |
2. Unlock Detection Software
Figure 3
3. Unlocked State Data Output Using Serial Data Output
In the LC72133, once an unlocked state occurs, the unlocked state serial data (UL) will not be reset until a data input
(or output) operation is performed. At the data output x point in Figure 3, although the VCO frequency has
stabilized (locked), since no data output has been performed since the divisor N was changed the unlocked state data
remains in the unlocked state. As a result, even though the frequency has stabilized (locked), the system remains
(from the standpoint of the data) in the unlocked state.
Therefore, the unlocked state data acquired at data output x, which occurs immediately after the divisor N was
changed, should be treated as a dummy data output and ignored. The second data output (data output ) and
following outputs are valid data.
Locked State Determination Flowchart
4. Directly Outputting Unlocked State Data from the DO Pin (Set by the DO pin control data)
Since the locking state (high = locked, low = unlocked) is output directly from the DO pin, the dummy data
processing described in section 3 above is not required. After changing the divisor N, the locking state can be
checked after waiting at least two reference frequency periods.
No. 5427-19/23
LC72133M, 72133V
A11938
CE
*
YES
NO
N
VCO
frequency
ERROR
Unlock (UL) serial
data input
Unlock detection
pin output
Data input
Data output
Old data
New data
Locked
Unlocked
Divisor N modification
(data input)
Dummy data output
Valid data output
Locked?
...............
Wait for at least two reference
frequency periods.
Valid data can be output at intervals
of one reference frequency period or
longer
Note: Locking state determination is more
reliable if it is based on reading valid
output data several times.
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