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參數資料
| 型號： | LC72133V |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁數： | 9/23頁 |
| 文件大小： | 147K |
| 代理商： | LC72133V |
2. IF Counter Operation
Before starting the IF count, the IF counter must be reset in advance by setting CTE in the serial data to 0.
The IF count is started by changing the CTE bit in the serial data from 0 to 1. The serial data is latched by the
LC72133 when the CE pin is dropped from high to low. The IF signal must be supplied to the IFIN pin in the period
between the point the CE pin goes low and the end of the wait time at the latest. Next, the value of the IF counter at
the end of the measurement period must be read out during the period that CTE is 1. This is because the IF counter is
reset when CTE is set to 0.
Note: When operating the IF counter, the control microprocessor must first check the state of the IF-IC SD (station
detect) signal and only after determining that the SD signal is present turn on IF buffer output and execute an
IF count operation. Autosearch techniques that use only the IF counter are not recommended, since it is
possible for IF buffer leakage output to cause incorrect stops at points where there is no station.
IFIN minimum input sensitivity standard
f (MHz)
Note: Values in parentheses are actual performance values presented as reference data.
No. 5427-17/23
LC72133M, 72133V
IFS
0.4
≤ f < 0.5
0.5
≤ f < 8
8
≤ f ≤ 12
1: Normal mode
70 mVrms
(0.5 to 5 mVrms)
(2 to 10 mVrms)
0: Degradation mode
100 mVrms
(10 to 15 mVrms)
(30 to 50 mVrms)
CE
IFIN
GT
A11935
Frequency
measurement
period
Data with CTE = 1
Wait time
Measurement
period
Count start
Count end (end-UC)
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