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參數資料
| 型號： | LC72133V |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁數： | 4/23頁 |
| 文件大小： | 147K |
| 代理商： | LC72133V |
Continued from preceding page.
3. DO Output Data (Serial Data Output)
OUT Mode
4. DO Output Data
No. 5427-12/23
LC72133M, 72133V
No.
Control block/data
Functions
Related data
IF counter control data
Note that if this value is set to zero the system enters input sensitivity degradation mode,
(11)
IFS
and the sensitivity is reduced to 10 to 30 mV rms.
* See the “IF Counter Operation” item for details.
LSI test data
LSI test data
TEST 0 to TEST 2
TEST0
(12)
TEST1
These values must all be set to 0.
TEST2
These test data are set to 0 automatically after the power-on reset.
(13)
DNC
Don’t care. This data must be set to 0.
No.
Control block/data
Functions
Related data
I/O port data
Latched from the pin states of the IO1 and IO2 I/O ports.
I2, I1
These values follow the pin states regardless of the input or output setting.
Data is latched at the point where the circuit enters data output mode (OUT mode).
I1
← IO1 pin state
High: 1
I2
← IO2 pin state
Low: 0
PLL unlock data
Latched from the state of the unlock detection circuit.
UL
← 0: Unlocked
UL
← 1: Locked or detection stopped mode
IF counter binary data
Latched from the value of the IF counter (20-bit binary counter).
C19 to C0
C19
← MSB of the binary counter
C0
← LSB of the binary counter
(1)
(2)
(3)
IOC1,
IOC2
UL0,
UL1
CTE,
GT0,
GT1
DI
01010100
DO
I2
(1)
IN-PORT
(2)
UNLOCK
(3)
IF-CTR
I1
6
UL
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
Address
A11921
6 : "0" data
First Data OUT
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