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參數資料
| 型號： | LC89057W-VF4-E |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, SQFP-48 |
| 文件頁數： | 18/61頁 |
| 文件大小： | 355K |
| 代理商： | LC89057W-VF4-E |
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LC89057W-VF4-E
No. 7202-25/61
8.4 Error Output Processing
8.4.1 Lock error, data error output (RERR)
RERR outputs an error flag when a PLL lock error or a data error occurs.
Non-PCM data reception can be treated as an error with the RESEL setting.
The RERR output conditions are set with RESTA. Since the PLL status can be output at all times, the PLL status
can be monitored at all times, even when the clock source is XIN.
8.4.2 PLL lock error
The PLL gets unlocked for input data that has lost bi-phase modulation regularity, or input data for which preambles
B, M, and W cannot be detected.
RERR goes "H" upon occurrence of a PLL lock error, and returns to "L" when data demodulation returns to normal
and "H" is maintained for between 45ms and 300ms.
The rising and falling edges of RERR are synchronized with RLRCK.
8.4.3 Input data parity error
Odd number of parity bits in input data errors and input parity errors are detected.
If an input parity error occurs 9 or more times in succession, RERR goes "H" indicating that the PLL is locked, and
after holding "H" for between 45ms and 300ms, it returns to "L".
The error flag output format for when an input parity error is output 8 times in succession can be selected with
REDER.
8.4.4 Other errors
Even if RERR goes "L", the channel status bits 24 to 27 (sampling frequency) are always fetched and the data of the
previous block is compared with the current data. Moreover, the input data sampling frequency is calculated from
the fs clock extracted from the input data, and fs calculation value comparison is performed as described above. If a
difference is detected, RERR is instantly made "H" and the same processing as for PLL lock errors is performed.
The PLL causes a lock error when the sampling frequency changes as described above. However, in order to
support sources with a variable sampling frequency (for example a CD player with a variable pitch function), it is
possible to perform a setting with FSERR so that no error flag is output if the sampling frequency variation falls
within the PLL capture range.
Moreover, the FSERR setting prevents fs calculation results for input data within the reception range set with
FSLIM0,1 from being reflected to the error flag, and if the PLL status changes to the locked status, it causes RERR
to go "L".
If a setting such that an error occurs when non-PCM data is input is performed with RESEL, RERR changes to "H"
output upon detection of non-PCM data input. At this time, the PLL locked status and various output clocks are
according to the input data, but the output data is muted.
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