
LC89057W-VF4-E
No. 7202-12/61
8 Description of Demodulation Function
The demodulation function operation settings are performed with RXOPR. The operating status is set as the initial
value.
8.1 Clocks
8.1.1 PLL (LPF)
A VCO (Voltage Controlled Oscillator) that can be stopped with PLLOPR is provided on chip and synchronization
to frequencies from 32kHz to 192kHz and transfer rate of 4MHz to 25MHz can be selected.
The PLL clock frequency is selected with PLLSEL. For systems with an input data sampling frequency of 105kHz
or lower, the initial setting of 512fs is recommended. Since the system clock RMCK output initial value is set to 1/2
of PLLSEL, the RMCK output is 256fs when a PLL clock frequency of 512fs is used.
For receptions systems with an input data sampling frequency higher than 105kHz, switch the PLL clock frequency
to 256fs. Since, if the same initial output setting as above is used, RMCK is 128fs, set PRESEL0,1 as needed.
LPF is a PLL loop filter pin. Connect the following resistance and capacitances by selecting the PLLSEL system
clock. Since PLLSEL switching involves a change in LPF loop filter constant, perform the PLLSEL setting prior to
bi-phase data input.
LPF
R0
C0
C1
Clock
512fs
256fs
R0
C0
C1
220
0.1
F
0.022
F
330
0.068
F
0.001
F
Figure 8.1. Loop Filter Configuration
8.1.2 Demodulation Function without Using PLL (TMCK)
The LC89057W-VF4-E has a function to process input bi-phase data using an external clock (external
synchronization function). In normal demodulation processing, the clock is generated in synchronization with data
by the built-in PLL and data processing is performed using this clock. In contrast, in the LC89057W-VF4-E, data
processing is also possible to perform data processing by supplying a data synchronized clock instead of the clock
generated by the PLL via an independent transmission path.
To use the external synchronization function, set the demodulation function without using PLL with EXSYNC, and
after setting the 256fs clock with PLLSEL, and PLLSEL setting frequency 1/1 with PRSEL0,1, input the 256fs
clock synchronized with the input data to TMCK. As a result of these settings, the same operation as PLL
demodulation processing when the 256fs clock is set is performed. Also, do not connect anything to LPF. No loop
filter is required either.
Complete the above external synchronization function settings prior to bi-phase data input. Also pay attention to the
bandwidth of clock transmission path.
A high-precision clock system using an external PLL can also be configured by using the external synchronization
function.