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參數資料
| 型號： | MBM30LV0128-PFTR |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | 128 M (16 M X 8) BIT NAND-type |
| 中文描述： | 16M X 8 FLASH 2.7V PROM, PDSO48 |
| 封裝： | PLASTIC, REVERSE, TSOP-48 |
| 文件頁數： | 37/43頁 |
| 文件大小： | 397K |
| 代理商： | MBM30LV0128-PFTR |
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MBM30LV0064
37
(15) Inhibit RE Toggling during Busy State
The RE input cannot be allowed to toggle during the period that a read data transfer operation is in process
(busy state).
If the RE input toggles during that period, the internal column address will increment.
(16) Restriction on Toggling the WE
The WE input cannot be allowed to toggle past the end of page (byte 511 with SE high or byte 527 with SE low)
during an input data operation. If the WE input toggles past the end of page, the internal address counter will
wrap around to the begging of the page and overwrite the information previously there.
(17) Reading Past Last Device Page
When the last byte in the last page of the device is read, the internal address counter will wrap around to the
fist page in the device.
CLE
CE
WE
ALE
RE
I/O0
to I/O7
R/B
Starting Address Y
Toggling X times (
→
Inhibiting)
Start from column
address Y + X
80h
10h
70h
CLE
CE
WE
ALE
R/B
RE
D
IN
*
D
IN
Output
Status
I/O0
to I/O7
*: DIN for address 511 with SE = "H" or
527 with SE = "L"
Inhibit toggling
: V
IH
or V
IL
: Invalid Data
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