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參數(shù)資料
| 型號(hào)： | MC68C912B32CFU8 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-Bit Microcontroller |
| 中文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁(yè)數(shù)： | 67/128頁(yè) |
| 文件大小： | 748K |
| 代理商： | MC68C912B32CFU8 |
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MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
67
PPOL3 — PWM Channel 3 Polarity
0 = Channel 3 output is low at the beginning of the clock cycle; high when the duty count is reached.
1 = Channel 3 output is high at the beginning of the clock cycle; low when the duty count is reached.
PPOL2 — PWM Channel 2 Polarity
0 = Channel 2 output is low at the beginning of the clock cycle; high when the duty count is reached.
1 = Channel 2 output is high at the beginning of the clock cycle; low when the duty count is reached.
PPOL1 — PWM Channel 1 Polarity
0 = Channel 1 output is low at the beginning of the clock cycle; high when the duty count is reached.
1 = Channel 1 output is high at the beginning of the clock cycle; low when the duty count is reached.
PPOL0 — PWM Channel 0 Polarity
0 = Channel 0 output is low at the beginning of the clock cycle; high when the duty count is reached.
1 = Channel 0 output is high at the beginning of the clock cycle; low when the duty count is reached.
Depending on the polarity bit, the duty registers may contain the count of either the high time or the low
time. If the polarity bit is zero and left alignment is selected, the duty registers contain a count of the low
time. If the polarity bit is one, the duty registers contain a count of the high time. For center-aligned op-
eration the high or low time is multiplied by two.
Setting any of the PWENx bits causes the associated port P line to become an output regardless of the
state of the associated data direction register (DDRP) bit. This does not change the state of the data
direction bit. When PWENx returns to zero, the data direction bit controls I/O direction. On the front end
of the PWM channel, the scaler clock is enabled to the PWM circuit by the PWENx enable bit being
high. When all four PWM channels are disabled, the prescaler counter shuts off to save power. There
is an edge-synchronizing gate circuit to guarantee that the clock will only be enabled or disabled at an
edge.
Read and write anytime.
PWEN3 — PWM Channel 3 Enable
The pulse modulated signal will be available at port P, bit 3 when its clock source begins its next cycle.
0 = Channel 3 is disabled.
1 = Channel 3 is enabled.
PWEN2 — PWM Channel 2 Enable
The pulse modulated signal will be available at port P, bit 2 when its clock source begins its next cycle.
0 = Channel 2 is disabled.
1 = Channel 2 is enabled.
PWEN1 — PWM Channel 1 Enable
The pulse modulated signal will be available at port P, bit 1 when its clock source begins its next cycle.
0 = Channel 1 is disabled.
1 = Channel 1 is enabled.
PWEN0 — PWM Channel 0 Enable
The pulse modulated signal will be available at port P, bit 0 when its clock source begins its next cycle.
0 = Channel 0 is disabled.
1 = Channel 0 is enabled.
PWEN
— PWM Enable
$0042
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
PWEN3
PWEN2
PWEN1
PWEN0
RESET:
0
0
0
0
0
0
0
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68C912B32FU8 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:16-Bit Microcontroller |
| MC68CK16Z1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series |
| MC68CK16Z1CAG16 | 功能描述:16位微控制器 - MCU 16BIT 1KRAM 32KHZ CRYSTAL RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
| MC68CK16Z1CAG16 | 制造商:Freescale Semiconductor 功能描述:Microcontroller |
| MC68CK16Z1CFC16 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series |
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