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參數(shù)資料
型號(hào): MC68HC05P18A
廠商: Motorola, Inc.
英文描述: Low Cost HCMOS Microcontroller(低成本、8位HCMOS微控制器)
中文描述: 低成本HCMOS微控制器(低成本,8位HCMOS微控制器)
文件頁(yè)數(shù): 68/130頁(yè)
文件大小: 1200K
代理商: MC68HC05P18A
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L
G
R
16-Bit Timer
Technical Data
MC68HC05P18A
68
16-Bit Timer
MOTOROLA
8.4 Output Compare
The output compare function may be used to generate an output
waveform and/or as an elapsed time indicator. All of the bits in the output
compare register pair, OCRH/OCRL, are readable and writable and are
not altered by the 16-bit timer’s control logic. Reset does not affect the
contents of these registers. If the output compare function is not utilized,
its registers may be used for data storage. See
Figure 8-6
.
The contents of the output compare registers are compared with the
contents of the free-running counter once every four PH2 clock cycles.
If a match is found, the output compare flag bit (OCF) is set and the
output level bit (OLVL) is clocked to the output latch. The values in the
output compare registers and output level bit should be changed after
each successful comparison to control an output waveform or to
establish a new elapsed timeout. An interrupt can also accompany a
successful output compare if the output compare interrupt enable bit
(OCIE) is set.
After a CPU write cycle to the MSB of the output compare register pair
(OCRH), the output compare function is inhibited until the LSB (OCRL)
is written. Both bytes must be written if the MSB is written. A write made
only to the LSB will not inhibit the compare function. The free-running
Address:
$0016
Bit 7
6
5
4
3
2
1
Bit 0
Read:
OCRH7
OCRH6
OCRH5
OCRH4
OCRH3
OCRH2
OCRH1
OCRH0
Write:
Reset:
Unaffected by reset
Address:
$0017
Bit 7
6
5
4
3
2
1
Bit 0
Read:
OCRL7
OCRL6
OCRL5
OCRL4
OCRL3
OCRL2
OCRL1
OCRL0
Write:
Reset:
Unaffected by reset
Figure 8-6. Output Compare Registers (OCRH/OCRL)
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