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參數資料
| 型號： | MC68HC705V8 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數： | 11/28頁 |
| 文件大小： | 220K |
| 代理商： | MC68HC705V8 |
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AN1224/D
MOTOROLA
11
Figure 4. MC68HC705V8 Reset Subroutine
Following a reset of the MC68HC705V8, three MCU registers are initialized for use by these driver
routines. The miscellaneous (MISC) register is initialized with output compare disabled and power down
control enabled, enabling the primary voltage regulator. The MDLC control register (MCR) is initialized with
receive block mode disabled, R1:0 adjusted for 4.19 MHz oscillator, interrupts enabled, and wait clock
mode disabled.
In this example bits 3 and 2 of the MCR are also set. This is necessary for this
software to be run on the M68HC05V8EVS
. These bits will be ignored by the MC68HC705V8 running in
Single-Chip Mode. This routine also initializes the core timer control and status register (CTCSR) to set the
RTI interrupt rate to once every 2
13
/E, or every 3.90 ms. At this time, RTI interrupts are not enabled.
Next, the physical address of the node is stored in MCU RAM location "source". This RAM location
corresponds to the third byte in the RAM transmit buffer. This ensures that the physical address of the
node will be transmitted as the third byte of each message transmitted by the MDLC, as required by the
three-byte message header format outlined in SAE J1850. The MCU RAM location "rticnt" is then cleared,
preparing it for use with the MDLC message transmit subroutine.
The only other MCU RAM initialization required is the initialization of the received message buffer pointers
(RMBP) pointing to the functional message receive buffers. Each RMBP is loaded with the starting address
of a corresponding functional message receive buffer. In this example, there are four functional message
receive buffers, one for each functional message I.D. However, the number of functional I.D.s, and buffers,
can be increased by the user, with the only limit being the amount of RAM available and the amount of time
the user can spend sorting received messages.
Once this is complete and the I-bit is cleared, enabling interrupts, the MC68HC705V8 is loaded and ready
for multiplex communication. Refer to
Figure 4 MC68HC705V8 Reset Subroutine
for a graphical
representation of the reset sequence.
LOAD $22 INTO MCR
TO ENABLE MDLC
INTERRUPTS, SET
WAIT CLOCK MODE,
AND SELECT COMM.
RATE BASED ON 4.2
MHZ OSCILLATOR
LOAD $02 INTO
CTCSR TO SET
RTI RATE = 2
13
/E
BEGIN INITIALIZATION
SUBROUTINE
LOAD NODE
PHYSICAL ADDRESS
INTO MCU RAM
LOCATION "source"
CLEAR MCU RAM
LOCATION "rticnt"
LOAD STARTING
LOCATION OF EACH
RECEIVE BUFFER
INTO
CORRESPONDING
RECEIVE BUFFER
POINTER
WRITE $00 INTO
COPR TO RESET
WATCHDOG TIMER
RETURN FROM INIT.
SUBROUTINE
CLEAR I-BIT TO
ALLOW INTERRUPTS
When running this software on
the M68HC05V8EVS or the
MMDS05V8, bits 2 and 3 of the
MCR must also be set for the
MDLC module to function
properly.
LOAD $01 INTO MISC
TO ENSURE PRIMARY
REGULATOR REMAINS
ENABLED
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