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參數資料
| 型號： | MC68HC705V8 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數： | 26/28頁 |
| 文件大小： | 220K |
| 代理商： | MC68HC705V8 |
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MOTOROLA
26
AN1224/D
133E [03] B611 451 get_msg: lda mrsr ;Read received message byte count
452
1340 [02] A003 453 sub #$03 ;Subtract $03 to account for message header
454
1342 [04] B74F 455 sta byte_cnt ;And store in temporary storage
456
1344 [04] EB5A 457 add fmsg1,x ;Add starting address of appropriate
458 ;RAM message buffer to get ending address
459
1346 [03] 4A 460 deca ;Decrement to get correct address index
461
1347 [04] B74E 462 sta buff_ndx ;and store in temporary storage
463
1349 [03] BE4F 464 next_byt: ldx byte_cnt ;Then load message byte count into X-reg.
465
134B [04] E636 466 lda rxdata2,x ;Read message data byte from MDLC Rx buffer
467
134D [03] BE4E 468 ldx buff_ndx ;Now load message buffer index into X-reg.
469
134F [04] F7 470 sta ,x ;and store data byte into RAM message buffer
471
1350 [05] 3A4E 472 dec buff_ndx ;Decrement message buffer index
473
1352 [05] 3A4F 474 dec byte_cnt ;Decrement received byte count
475
1354 [03] 26F3 476 bne next_byt ;If not zero, go get next byte
477
1356 [04] B711 478 rxdone: sta mrsr ;Write data in Acc. into MRSR to clear
479 ;RXMS interrupt
480
481 *** Tx Message Successful Interrupt Handling Routine ***
482
1358 [05] 070F0E 483 txint: brclr txms,msr,mdlcclr ;Check to see if a Tx interrupt
484 ;is pending - if not, go return
485 ;from the interrupt
486
135B [05] 3F41 487 clr rticnt ;Clear RTI Counter register
488
135D [05] 1908 489 bclr rtie,ctcsr ;Then disable the RTI interrupt
490
135F [02] A600 491 lda #$00 ;Write $00 into the MTCR
1361 [04] B710 492 sta mtcr ;to clear TXMS interrupt
493
1363 [05] 050F03 494 brclr rxms,msr,mdlcclr ;If Rx interrupt is not pending,
495 ;then finish up interrupt routine
496
1366 [03] CC1306 497 jmp rxint ;Otherwise, go check out the
498 ;pending receive interrupt
499
1369 [09] 80 500 mdlcclr: rti ;Return from interrupt
501
502 ***************************************************************************
503 * Core Timer Interrupt Service Routine *
504 ***************************************************************************
505
506 ******************************************************************
507 * This routine handles the Real Time Interrupt (RTI) interrupts *
508 * enabled by the routine which initiates MDLC transmissions. The *
509 * RTI interrupts occur every 3.9ms. Following the initiation of *
510 * a transmission by the MDLC module, if the TXMS bit is not set *
511 * before 9 RTI interrupts are recorded (approximately 30ms), the *
512 * transmission will be aborted. This routine records and counts *
513 * the number of RTI interrupts, and when the count reaches 9, *
514 * the message transmission is aborted automatically by software. *
515 ******************************************************************
516
1000 517 org ctimer
518
519 *** RTI Interrupt Service Routine ***
520
1000 [05] 1408 521 bset rtfc,ctcsr ;Clear RTI interrupt flag
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