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參數資料
| 型號： | MC68HC705V8 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數： | 4/28頁 |
| 文件大小： | 220K |
| 代理商： | MC68HC705V8 |
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MOTOROLA
4
AN1224/D
arbitration begins with the first bit following the SOF delimiter, and continues with each bit thereafter.
Whenever a transmitting node detects a dominant bit while transmitting a recessive bit, it loses arbitration,
and immediately stops transmitting. This is known as "bitwise" arbitration. Since an active bit dominates a
passive bit (a "0" dominates a "1"), the frame with the lowest value will have the highest priority, and will
always win arbitration, i.e., a frame with priority 000 will win arbitration over a frame with priority 001. This
method of arbitration will work regardless of how many bits of priority encoding are contained in the frame.
Frequently, messaging strategies are utilized which ensure that all arbitration is resolved by the end of the
frame header.
In-Frame Response
The optional in-frame response (IFR) portion of a frame follows the EOD delimiter, and contains one of
three types of information. The first type of IFR contains a single I.D. byte from a single receiver, indicating
that at least one node received the frame. The I.D. byte is usually the physical address of the responding
node. The second type of IFR contains multiple I.D. bytes from multiple receivers, indicating which
receivers actually received the frame. In this case, the number of response bytes is limited only by the
overall J1850 frame length constraints. The third type of IFR contains data bytes, with or without a CRC
byte, from a single receiver. This type of IFR usually occurs during the IFR portion of a frame in which that
data is requested. The CRC byte, if included in the IFR, is calculated and decoded in an identical manner
to the frame CRC, except the transmitter and receiver roles are reversed. In VPW modulation, the in-frame
response byte is preceded by a normalization bit, which is required to return the bus to the dominant state
prior to transmitting the first bit of the IFR.
Modulation
As previously mentioned, J1850 frames can be transmitted using two different modulation techniques,
pulse width modulation (PWM) or variable pulse width modulation (VPW). The modulation technique used
is dependent upon the desired transmission bit rate and the physical makeup of the bus. The PWM
technique is primarily used with a bit rate of 41.7 kbps, and a bus consisting of a differential twisted pair.
VPW modulation is used with a bit rate of 10.4 kbps and a single wire bus.
For more detailed information on the features of J1850, refer to
SAE Recommended Practice J1850-Class
B Data Communication Network Interface
. Because this document is still subject to modification, the user
should ensure that the most recent version is referenced.
MC68HC705V8 MICROCONTROLLER
The MC68HC705V8 MCU is a multipurpose HCMOS MCU based on the industry standard MC68HC05
CPU. The available user memory on the MC68HC705V8 includes 12K of EPROM, 512 bytes of RAM
(including stack) and 128 bytes of EEPROM. In addition to the MDLC module, other features include an
internal power supply, a serial peripheral interface port, a 6-bit pulse width modulation port, a 16-bit timer
with one input capture and one output compare, a multi-function core timer, a 16-channel 8-bit analog to
digital (A/D) converter and an onboard watchdog system (refer to
Figure 2 MC68HC705V8 Block
Diagram
). A few of the major features of the MC68HC705V8 are outlined below. For a detailed description
of the features and operation of the MC68HC705V8, refer to the
MC68HC705V8 Product Specification
.
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