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參數資料
| 型號： | MC68HC705V8 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數： | 24/28頁 |
| 文件大小： | 220K |
| 代理商： | MC68HC705V8 |
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MOTOROLA
24
AN1224/D
309 ***************************************************************************
310 ***** Subroutines *****
311 ***************************************************************************
312
313 *** MDLC Transmit Subroutine ***
314
315 **********************************************************************
316 * This subroutine transfers the data in the RAM transmit buffer into *
317 * the MDLC Tx buffer, loads the number of bytes to be transmitted *
318 * into the MTCR, initiating the message transmission, and then *
319 * enables the RTI interrupt to count RTI's until either the message *
320 * is transmitted successfully, or 30ms has passed. If 30ms passes *
321 * without the message transmitting successfully, the message will *
322 * be aborted automatically by the software. *
323 **********************************************************************
324
202A [03] BE42 325 transmit: ldx txcount ;Load the number of bytes to be transmitted
326 ;into the X-register
327
202C [03] 5A 328 nexttx: decx ;Now decrement X to get it to the correct
329 ;value to begin an indexed transfer of the
330 ;data from RAM into the MDLC Tx buffer
331
202D [04] E643 332 lda txbuf,x ;Load message data byte (last byte first)
202F [05] E720 333 sta txdata0,x ;into the MDLC Tx register
334
2031 [03] 5D 335 tstx ;Test the X-Register to see if it is 0
336
2032 [03] 26F8 337 bne nexttx ;If X<>0, indicating the last byte has not
338 ;been transferred, then go get the next byte
339
2034 [03] B642 340 lda txcount ;Otherwise, load Tx byte count into Acc.
341
2036 [04] B710 342 sta mtcr ;Then store in MTCR, initiating transmission
343
2038 [05] 1408 344 bset rtfc,ctcsr ;Clear RTI interrupt flag, in case it is set
345
203A [05] 1808 346 bset rtie,ctcsr ;Enable RTI interrupt to track how
347 ;long the transmission is pending
348
203C [06] 81 349 rts ;Then return from subroutine
350
351 ***************************************************************************
352 ***** MDLC Interrupt Routine Service *****
353 ***************************************************************************
354
355 **********************************************************************
356 * The MDLC interrupt service routine handles both the transmit and *
357 * receive interrupts of the CPU generated by the MDLC module. When a *
358 * receive interrupt is serviced, the software automatically checks *
359 * the message type of the received message. If it is a physically *
360 * addressed message, the target address of the message is compared *
361 * to the node address, and if it matches, the message data bytes and *
362 * source address are retrieved and stored in RAM. If it is a funct- *
363 * ionally address message, the target address is compared to 4 pre- *
364 * viously defined target addresses and if there is a match, the data *
365 * bytes of the message are stored in that message ID's corresponding *
366 * RAM buffer. The source or target address are not retained, since *
367 * it is assumed that the receiver must already know what the message *
368 * pertains to. *
369 * When a transmit interrupt occurs, the MDLC module will *
370 * acknowledge the successful transmission by clearing the transmit *
371 * interrupt, and then disabling the RTI interrupt and clearing the *
372 * RTI counter register. The application is then ready for another *
373 * transmission. *
374 **********************************************************************
375
1300 376 org mdlc
377
1300 [05] 040F03 378 brset rxms,msr,rxint ;If an receive interrupt, go to
379 ;receive interrupt service routine
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